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![Kai Ye](/assets/img/avatar_default.png)
Add data cleared operation for sge data. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
289 lines
7.4 KiB
C
289 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 HiSilicon Limited. */
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "qm.h"
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#define HISI_ACC_SGL_SGE_NR_MIN 1
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#define HISI_ACC_SGL_NR_MAX 256
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#define HISI_ACC_SGL_ALIGN_SIZE 64
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#define HISI_ACC_MEM_BLOCK_NR 5
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struct acc_hw_sge {
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dma_addr_t buf;
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void *page_ctrl;
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__le32 len;
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__le32 pad;
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__le32 pad0;
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__le32 pad1;
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};
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/* use default sgl head size 64B */
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struct hisi_acc_hw_sgl {
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dma_addr_t next_dma;
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__le16 entry_sum_in_chain;
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__le16 entry_sum_in_sgl;
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__le16 entry_length_in_sgl;
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__le16 pad0;
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__le64 pad1[5];
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struct hisi_acc_hw_sgl *next;
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struct acc_hw_sge sge_entries[];
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} __aligned(1);
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struct hisi_acc_sgl_pool {
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struct mem_block {
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struct hisi_acc_hw_sgl *sgl;
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dma_addr_t sgl_dma;
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size_t size;
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} mem_block[HISI_ACC_MEM_BLOCK_NR];
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u32 sgl_num_per_block;
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u32 block_num;
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u32 count;
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u32 sge_nr;
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size_t sgl_size;
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};
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/**
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* hisi_acc_create_sgl_pool() - Create a hw sgl pool.
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* @dev: The device which hw sgl pool belongs to.
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* @count: Count of hisi_acc_hw_sgl in pool.
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* @sge_nr: The count of sge in hw_sgl
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*
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* This function creates a hw sgl pool, after this user can get hw sgl memory
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* from it.
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*/
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struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
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u32 count, u32 sge_nr)
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{
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u32 sgl_size, block_size, sgl_num_per_block, block_num, remain_sgl;
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struct hisi_acc_sgl_pool *pool;
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struct mem_block *block;
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u32 i, j;
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if (!dev || !count || !sge_nr || sge_nr > HISI_ACC_SGL_SGE_NR_MAX)
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return ERR_PTR(-EINVAL);
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sgl_size = sizeof(struct acc_hw_sge) * sge_nr +
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sizeof(struct hisi_acc_hw_sgl);
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/*
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* the pool may allocate a block of memory of size PAGE_SIZE * 2^(MAX_ORDER - 1),
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* block size may exceed 2^31 on ia64, so the max of block size is 2^31
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*/
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block_size = 1 << (PAGE_SHIFT + MAX_ORDER <= 32 ?
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PAGE_SHIFT + MAX_ORDER - 1 : 31);
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sgl_num_per_block = block_size / sgl_size;
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block_num = count / sgl_num_per_block;
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remain_sgl = count % sgl_num_per_block;
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if ((!remain_sgl && block_num > HISI_ACC_MEM_BLOCK_NR) ||
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(remain_sgl > 0 && block_num > HISI_ACC_MEM_BLOCK_NR - 1))
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return ERR_PTR(-EINVAL);
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pool = kzalloc(sizeof(*pool), GFP_KERNEL);
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if (!pool)
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return ERR_PTR(-ENOMEM);
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block = pool->mem_block;
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for (i = 0; i < block_num; i++) {
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block[i].sgl = dma_alloc_coherent(dev, block_size,
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&block[i].sgl_dma,
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GFP_KERNEL);
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if (!block[i].sgl) {
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dev_err(dev, "Fail to allocate hw SG buffer!\n");
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goto err_free_mem;
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}
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block[i].size = block_size;
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}
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if (remain_sgl > 0) {
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block[i].sgl = dma_alloc_coherent(dev, remain_sgl * sgl_size,
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&block[i].sgl_dma,
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GFP_KERNEL);
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if (!block[i].sgl) {
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dev_err(dev, "Fail to allocate remained hw SG buffer!\n");
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goto err_free_mem;
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}
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block[i].size = remain_sgl * sgl_size;
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}
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pool->sgl_num_per_block = sgl_num_per_block;
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pool->block_num = remain_sgl ? block_num + 1 : block_num;
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pool->count = count;
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pool->sgl_size = sgl_size;
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pool->sge_nr = sge_nr;
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return pool;
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err_free_mem:
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for (j = 0; j < i; j++) {
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dma_free_coherent(dev, block_size, block[j].sgl,
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block[j].sgl_dma);
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memset(block + j, 0, sizeof(*block));
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}
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kfree(pool);
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return ERR_PTR(-ENOMEM);
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}
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EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);
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/**
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* hisi_acc_free_sgl_pool() - Free a hw sgl pool.
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* @dev: The device which hw sgl pool belongs to.
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* @pool: Pointer of pool.
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*
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* This function frees memory of a hw sgl pool.
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*/
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void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool)
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{
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struct mem_block *block;
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int i;
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if (!dev || !pool)
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return;
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block = pool->mem_block;
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for (i = 0; i < pool->block_num; i++)
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dma_free_coherent(dev, block[i].size, block[i].sgl,
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block[i].sgl_dma);
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kfree(pool);
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}
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EXPORT_SYMBOL_GPL(hisi_acc_free_sgl_pool);
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static struct hisi_acc_hw_sgl *acc_get_sgl(struct hisi_acc_sgl_pool *pool,
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u32 index, dma_addr_t *hw_sgl_dma)
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{
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struct mem_block *block;
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u32 block_index, offset;
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if (!pool || !hw_sgl_dma || index >= pool->count)
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return ERR_PTR(-EINVAL);
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block = pool->mem_block;
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block_index = index / pool->sgl_num_per_block;
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offset = index % pool->sgl_num_per_block;
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*hw_sgl_dma = block[block_index].sgl_dma + pool->sgl_size * offset;
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return (void *)block[block_index].sgl + pool->sgl_size * offset;
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}
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static void sg_map_to_hw_sg(struct scatterlist *sgl,
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struct acc_hw_sge *hw_sge)
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{
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hw_sge->buf = sg_dma_address(sgl);
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hw_sge->len = cpu_to_le32(sg_dma_len(sgl));
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hw_sge->page_ctrl = sg_virt(sgl);
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}
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static void inc_hw_sgl_sge(struct hisi_acc_hw_sgl *hw_sgl)
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{
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u16 var = le16_to_cpu(hw_sgl->entry_sum_in_sgl);
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var++;
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hw_sgl->entry_sum_in_sgl = cpu_to_le16(var);
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}
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static void update_hw_sgl_sum_sge(struct hisi_acc_hw_sgl *hw_sgl, u16 sum)
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{
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hw_sgl->entry_sum_in_chain = cpu_to_le16(sum);
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}
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static void clear_hw_sgl_sge(struct hisi_acc_hw_sgl *hw_sgl)
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{
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struct acc_hw_sge *hw_sge = hw_sgl->sge_entries;
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int i;
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for (i = 0; i < le16_to_cpu(hw_sgl->entry_sum_in_sgl); i++) {
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hw_sge[i].page_ctrl = NULL;
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hw_sge[i].buf = 0;
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hw_sge[i].len = 0;
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}
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}
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/**
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* hisi_acc_sg_buf_map_to_hw_sgl - Map a scatterlist to a hw sgl.
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* @dev: The device which hw sgl belongs to.
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* @sgl: Scatterlist which will be mapped to hw sgl.
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* @pool: Pool which hw sgl memory will be allocated in.
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* @index: Index of hisi_acc_hw_sgl in pool.
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* @hw_sgl_dma: The dma address of allocated hw sgl.
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*
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* This function builds hw sgl according input sgl, user can use hw_sgl_dma
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* as src/dst in its BD. Only support single hw sgl currently.
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*/
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struct hisi_acc_hw_sgl *
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hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
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struct scatterlist *sgl,
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struct hisi_acc_sgl_pool *pool,
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u32 index, dma_addr_t *hw_sgl_dma)
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{
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struct hisi_acc_hw_sgl *curr_hw_sgl;
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dma_addr_t curr_sgl_dma = 0;
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struct acc_hw_sge *curr_hw_sge;
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struct scatterlist *sg;
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int i, sg_n, sg_n_mapped;
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if (!dev || !sgl || !pool || !hw_sgl_dma)
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return ERR_PTR(-EINVAL);
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sg_n = sg_nents(sgl);
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sg_n_mapped = dma_map_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
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if (!sg_n_mapped) {
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dev_err(dev, "DMA mapping for SG error!\n");
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return ERR_PTR(-EINVAL);
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}
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if (sg_n_mapped > pool->sge_nr) {
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dev_err(dev, "the number of entries in input scatterlist is bigger than SGL pool setting.\n");
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return ERR_PTR(-EINVAL);
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}
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curr_hw_sgl = acc_get_sgl(pool, index, &curr_sgl_dma);
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if (IS_ERR(curr_hw_sgl)) {
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dev_err(dev, "Get SGL error!\n");
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dma_unmap_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
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return ERR_PTR(-ENOMEM);
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}
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curr_hw_sgl->entry_length_in_sgl = cpu_to_le16(pool->sge_nr);
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curr_hw_sge = curr_hw_sgl->sge_entries;
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for_each_sg(sgl, sg, sg_n_mapped, i) {
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sg_map_to_hw_sg(sg, curr_hw_sge);
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inc_hw_sgl_sge(curr_hw_sgl);
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curr_hw_sge++;
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}
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update_hw_sgl_sum_sge(curr_hw_sgl, pool->sge_nr);
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*hw_sgl_dma = curr_sgl_dma;
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return curr_hw_sgl;
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}
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EXPORT_SYMBOL_GPL(hisi_acc_sg_buf_map_to_hw_sgl);
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/**
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* hisi_acc_sg_buf_unmap() - Unmap allocated hw sgl.
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* @dev: The device which hw sgl belongs to.
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* @sgl: Related scatterlist.
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* @hw_sgl: Virtual address of hw sgl.
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*
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* This function unmaps allocated hw sgl.
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*/
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void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
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struct hisi_acc_hw_sgl *hw_sgl)
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{
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if (!dev || !sgl || !hw_sgl)
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return;
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dma_unmap_sg(dev, sgl, sg_nents(sgl), DMA_BIDIRECTIONAL);
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clear_hw_sgl_sge(hw_sgl);
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hw_sgl->entry_sum_in_chain = 0;
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hw_sgl->entry_sum_in_sgl = 0;
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hw_sgl->entry_length_in_sgl = 0;
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}
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EXPORT_SYMBOL_GPL(hisi_acc_sg_buf_unmap);
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