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When the TRBE generates an IRQ, we stop the TRBE, collect the trace and then reprogram the TRBE with the updated buffer pointers, whenever possible. We might also leave the TRBE disabled, if there is not enough space left in the buffer. However, we do not touch the ETE at all during all of this. This means the ETE is only disabled when the event is disabled later (via irq_work). This is incorrect, as the ETE trace is still ON without actually being captured and may be routed to the ATB (even if it is for a short duration). So, we move the CPU into trace prohibited state always before disabling the TRBE, upon entering the IRQ handler. The state is restored if the TRBE is enabled back. Otherwise the trace remains prohibited. Since, the ETM/ETE driver now controls the TRFCR_EL1 per session, the tracing can be restored/enabled back when the event is rescheduled in. Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210923143919.2944311-6-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
33 lines
686 B
C
33 lines
686 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Arm v8 Self-Hosted trace support.
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*
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* Copyright (C) 2021 ARM Ltd.
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*/
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#ifndef __CORESIGHT_SELF_HOSTED_TRACE_H
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#define __CORESIGHT_SELF_HOSTED_TRACE_H
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#include <asm/sysreg.h>
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static inline u64 read_trfcr(void)
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{
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return read_sysreg_s(SYS_TRFCR_EL1);
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}
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static inline void write_trfcr(u64 val)
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{
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write_sysreg_s(val, SYS_TRFCR_EL1);
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isb();
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}
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static inline u64 cpu_prohibit_trace(void)
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{
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u64 trfcr = read_trfcr();
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/* Prohibit tracing at EL0 & the kernel EL */
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write_trfcr(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE));
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/* Return the original value of the TRFCR */
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return trfcr;
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}
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#endif /* __CORESIGHT_SELF_HOSTED_TRACE_H */
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