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![Chunfeng Yun](/assets/img/avatar_default.png)
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-5-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
200 lines
5.1 KiB
C
200 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (c) 2017 NXP. */
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#define PHY_CTRL0 0x0
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#define PHY_CTRL0_REF_SSP_EN BIT(2)
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#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5)
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#define PHY_CTRL0_FSEL_24M 0x2a
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#define PHY_CTRL1 0x4
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#define PHY_CTRL1_RESET BIT(0)
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#define PHY_CTRL1_COMMONONN BIT(1)
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#define PHY_CTRL1_ATERESET BIT(3)
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#define PHY_CTRL1_VDATSRCENB0 BIT(19)
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#define PHY_CTRL1_VDATDETENB0 BIT(20)
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#define PHY_CTRL2 0x8
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#define PHY_CTRL2_TXENABLEN0 BIT(8)
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#define PHY_CTRL2_OTG_DISABLE BIT(9)
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#define PHY_CTRL6 0x18
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#define PHY_CTRL6_ALT_CLK_EN BIT(1)
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#define PHY_CTRL6_ALT_CLK_SEL BIT(0)
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struct imx8mq_usb_phy {
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struct phy *phy;
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struct clk *clk;
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void __iomem *base;
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struct regulator *vbus;
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};
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static int imx8mq_usb_phy_init(struct phy *phy)
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{
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struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
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u32 value;
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value = readl(imx_phy->base + PHY_CTRL1);
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value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 |
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PHY_CTRL1_COMMONONN);
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value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
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writel(value, imx_phy->base + PHY_CTRL1);
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value = readl(imx_phy->base + PHY_CTRL0);
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value |= PHY_CTRL0_REF_SSP_EN;
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writel(value, imx_phy->base + PHY_CTRL0);
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value = readl(imx_phy->base + PHY_CTRL2);
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value |= PHY_CTRL2_TXENABLEN0;
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writel(value, imx_phy->base + PHY_CTRL2);
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value = readl(imx_phy->base + PHY_CTRL1);
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value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
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writel(value, imx_phy->base + PHY_CTRL1);
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return 0;
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}
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static int imx8mp_usb_phy_init(struct phy *phy)
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{
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struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
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u32 value;
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/* USB3.0 PHY signal fsel for 24M ref */
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value = readl(imx_phy->base + PHY_CTRL0);
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value &= ~PHY_CTRL0_FSEL_MASK;
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value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
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writel(value, imx_phy->base + PHY_CTRL0);
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/* Disable alt_clk_en and use internal MPLL clocks */
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value = readl(imx_phy->base + PHY_CTRL6);
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value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
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writel(value, imx_phy->base + PHY_CTRL6);
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value = readl(imx_phy->base + PHY_CTRL1);
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value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
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value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
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writel(value, imx_phy->base + PHY_CTRL1);
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value = readl(imx_phy->base + PHY_CTRL0);
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value |= PHY_CTRL0_REF_SSP_EN;
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writel(value, imx_phy->base + PHY_CTRL0);
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value = readl(imx_phy->base + PHY_CTRL2);
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value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
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writel(value, imx_phy->base + PHY_CTRL2);
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udelay(10);
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value = readl(imx_phy->base + PHY_CTRL1);
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value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
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writel(value, imx_phy->base + PHY_CTRL1);
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return 0;
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}
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static int imx8mq_phy_power_on(struct phy *phy)
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{
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struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
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int ret;
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ret = regulator_enable(imx_phy->vbus);
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if (ret)
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return ret;
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return clk_prepare_enable(imx_phy->clk);
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}
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static int imx8mq_phy_power_off(struct phy *phy)
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{
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struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
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clk_disable_unprepare(imx_phy->clk);
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regulator_disable(imx_phy->vbus);
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return 0;
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}
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static const struct phy_ops imx8mq_usb_phy_ops = {
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.init = imx8mq_usb_phy_init,
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.power_on = imx8mq_phy_power_on,
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.power_off = imx8mq_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct phy_ops imx8mp_usb_phy_ops = {
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.init = imx8mp_usb_phy_init,
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.power_on = imx8mq_phy_power_on,
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.power_off = imx8mq_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id imx8mq_usb_phy_of_match[] = {
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{.compatible = "fsl,imx8mq-usb-phy",
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.data = &imx8mq_usb_phy_ops,},
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{.compatible = "fsl,imx8mp-usb-phy",
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.data = &imx8mp_usb_phy_ops,},
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{ }
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};
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MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
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static int imx8mq_usb_phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct imx8mq_usb_phy *imx_phy;
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const struct phy_ops *phy_ops;
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imx_phy = devm_kzalloc(dev, sizeof(*imx_phy), GFP_KERNEL);
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if (!imx_phy)
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return -ENOMEM;
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imx_phy->clk = devm_clk_get(dev, "phy");
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if (IS_ERR(imx_phy->clk)) {
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dev_err(dev, "failed to get imx8mq usb phy clock\n");
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return PTR_ERR(imx_phy->clk);
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}
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imx_phy->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(imx_phy->base))
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return PTR_ERR(imx_phy->base);
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phy_ops = of_device_get_match_data(dev);
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if (!phy_ops)
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return -EINVAL;
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imx_phy->phy = devm_phy_create(dev, NULL, phy_ops);
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if (IS_ERR(imx_phy->phy))
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return PTR_ERR(imx_phy->phy);
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imx_phy->vbus = devm_regulator_get(dev, "vbus");
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if (IS_ERR(imx_phy->vbus))
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return PTR_ERR(imx_phy->vbus);
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phy_set_drvdata(imx_phy->phy, imx_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver imx8mq_usb_phy_driver = {
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.probe = imx8mq_usb_phy_probe,
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.driver = {
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.name = "imx8mq-usb-phy",
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.of_match_table = imx8mq_usb_phy_of_match,
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}
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};
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module_platform_driver(imx8mq_usb_phy_driver);
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MODULE_DESCRIPTION("FSL IMX8MQ USB PHY driver");
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MODULE_LICENSE("GPL");
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