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09e872d558
Without that patch if you use specific resolutions like 1280x1024, I can see distortion in the output. It seems as if the frequency for updating the pixel of the image is out of sync. For initialization tmds needs to be active, but can be disabled after init to fix blurry display Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
249 lines
8.8 KiB
C
249 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Chunhui Dai <chunhui.dai@mediatek.com>
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*/
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#include "phy-mtk-hdmi.h"
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#define HDMI_CON0 0x00
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#define RG_HDMITX_DRV_IBIAS 0
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#define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0)
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#define RG_HDMITX_EN_SER 12
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#define RG_HDMITX_EN_SER_MASK (0x0f << 12)
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#define RG_HDMITX_EN_SLDO 16
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#define RG_HDMITX_EN_SLDO_MASK (0x0f << 16)
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#define RG_HDMITX_EN_PRED 20
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#define RG_HDMITX_EN_PRED_MASK (0x0f << 20)
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#define RG_HDMITX_EN_IMP 24
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#define RG_HDMITX_EN_IMP_MASK (0x0f << 24)
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#define RG_HDMITX_EN_DRV 28
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#define RG_HDMITX_EN_DRV_MASK (0x0f << 28)
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#define HDMI_CON1 0x04
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#define RG_HDMITX_PRED_IBIAS 18
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#define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18)
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#define RG_HDMITX_PRED_IMP (0x01 << 22)
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#define RG_HDMITX_DRV_IMP 26
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#define RG_HDMITX_DRV_IMP_MASK (0x3f << 26)
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#define HDMI_CON2 0x08
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#define RG_HDMITX_EN_TX_CKLDO (0x01 << 0)
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#define RG_HDMITX_EN_TX_POSDIV (0x01 << 1)
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#define RG_HDMITX_TX_POSDIV 3
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#define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3)
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#define RG_HDMITX_EN_MBIAS (0x01 << 6)
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#define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7)
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#define HDMI_CON4 0x10
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#define RG_HDMITX_RESERVE_MASK (0xffffffff << 0)
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#define HDMI_CON6 0x18
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#define RG_HTPLL_BR 0
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#define RG_HTPLL_BR_MASK (0x03 << 0)
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#define RG_HTPLL_BC 2
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#define RG_HTPLL_BC_MASK (0x03 << 2)
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#define RG_HTPLL_BP 4
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#define RG_HTPLL_BP_MASK (0x0f << 4)
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#define RG_HTPLL_IR 8
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#define RG_HTPLL_IR_MASK (0x0f << 8)
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#define RG_HTPLL_IC 12
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#define RG_HTPLL_IC_MASK (0x0f << 12)
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#define RG_HTPLL_POSDIV 16
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#define RG_HTPLL_POSDIV_MASK (0x03 << 16)
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#define RG_HTPLL_PREDIV 18
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#define RG_HTPLL_PREDIV_MASK (0x03 << 18)
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#define RG_HTPLL_FBKSEL 20
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#define RG_HTPLL_FBKSEL_MASK (0x03 << 20)
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#define RG_HTPLL_RLH_EN (0x01 << 22)
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#define RG_HTPLL_FBKDIV 24
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#define RG_HTPLL_FBKDIV_MASK (0x7f << 24)
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#define RG_HTPLL_EN (0x01 << 31)
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#define HDMI_CON7 0x1c
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#define RG_HTPLL_AUTOK_EN (0x01 << 23)
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#define RG_HTPLL_DIVEN 28
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#define RG_HTPLL_DIVEN_MASK (0x07 << 28)
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static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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usleep_range(80, 100);
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return 0;
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}
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static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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usleep_range(80, 100);
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}
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static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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u32 pos_div;
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if (rate <= 64000000)
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pos_div = 3;
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else if (rate <= 128000000)
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pos_div = 2;
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else
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pos_div = 1;
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
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RG_HTPLL_IC_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
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RG_HTPLL_IR_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
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RG_HDMITX_TX_POSDIV_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
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RG_HTPLL_FBKSEL_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
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RG_HTPLL_FBKDIV_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
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RG_HTPLL_DIVEN_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
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RG_HTPLL_BP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
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RG_HTPLL_BC_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
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RG_HTPLL_BR_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
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RG_HDMITX_PRED_IBIAS_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
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RG_HDMITX_DRV_IMP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
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RG_HDMITX_DRV_IBIAS_MASK);
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return 0;
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}
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static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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unsigned long out_rate, val;
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val = (readl(hdmi_phy->regs + HDMI_CON6)
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& RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
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switch (val) {
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case 0x00:
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out_rate = parent_rate;
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break;
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case 0x01:
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out_rate = parent_rate / 2;
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break;
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default:
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out_rate = parent_rate / 4;
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break;
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}
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val = (readl(hdmi_phy->regs + HDMI_CON6)
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& RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
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out_rate *= (val + 1) * 2;
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val = (readl(hdmi_phy->regs + HDMI_CON2)
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& RG_HDMITX_TX_POSDIV_MASK);
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out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
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if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
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out_rate /= 5;
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return out_rate;
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}
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static const struct clk_ops mtk_hdmi_phy_pll_ops = {
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.prepare = mtk_hdmi_pll_prepare,
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.unprepare = mtk_hdmi_pll_unprepare,
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.set_rate = mtk_hdmi_pll_set_rate,
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.round_rate = mtk_hdmi_pll_round_rate,
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.recalc_rate = mtk_hdmi_pll_recalc_rate,
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};
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static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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usleep_range(80, 100);
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}
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static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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usleep_range(80, 100);
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}
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struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
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.flags = CLK_SET_RATE_GATE,
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.pll_default_off = true,
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.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
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.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
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.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
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};
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MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
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MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
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MODULE_LICENSE("GPL v2");
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