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![Chunfeng Yun](/assets/img/avatar_default.png)
Use devm_platform_ioremap_resource to simplify code Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629191987-20774-7-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
211 lines
5.1 KiB
C
211 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*/
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#include "phy-mtk-hdmi.h"
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static int mtk_hdmi_phy_power_on(struct phy *phy);
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static int mtk_hdmi_phy_power_off(struct phy *phy);
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static const struct phy_ops mtk_hdmi_phy_dev_ops = {
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.power_on = mtk_hdmi_phy_power_on,
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.power_off = mtk_hdmi_phy_power_off,
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.owner = THIS_MODULE,
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};
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void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp &= ~bits;
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writel(tmp, reg);
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}
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void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp |= bits;
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writel(tmp, reg);
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}
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void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 val, u32 mask)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp = (tmp & ~mask) | (val & mask);
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writel(tmp, reg);
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}
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inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_hdmi_phy, pll_hw);
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}
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static int mtk_hdmi_phy_power_on(struct phy *phy)
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{
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struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
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int ret;
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ret = clk_prepare_enable(hdmi_phy->pll);
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if (ret < 0)
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return ret;
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hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
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return 0;
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}
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static int mtk_hdmi_phy_power_off(struct phy *phy)
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{
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struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
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hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
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clk_disable_unprepare(hdmi_phy->pll);
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return 0;
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}
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static const struct phy_ops *
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mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
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{
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if (hdmi_phy && hdmi_phy->conf &&
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hdmi_phy->conf->hdmi_phy_enable_tmds &&
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hdmi_phy->conf->hdmi_phy_disable_tmds)
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return &mtk_hdmi_phy_dev_ops;
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if (hdmi_phy)
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dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
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return NULL;
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}
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static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
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struct clk_init_data *clk_init)
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{
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clk_init->flags = hdmi_phy->conf->flags;
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clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
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}
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static int mtk_hdmi_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_hdmi_phy *hdmi_phy;
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struct clk *ref_clk;
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const char *ref_clk_name;
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struct clk_init_data clk_init = {
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.num_parents = 1,
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.parent_names = (const char * const *)&ref_clk_name,
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};
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struct phy *phy;
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struct phy_provider *phy_provider;
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int ret;
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hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
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if (!hdmi_phy)
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return -ENOMEM;
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hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(hdmi_phy->regs))
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return PTR_ERR(hdmi_phy->regs);
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ref_clk = devm_clk_get(dev, "pll_ref");
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if (IS_ERR(ref_clk)) {
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ret = PTR_ERR(ref_clk);
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dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
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ret);
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return ret;
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}
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ref_clk_name = __clk_get_name(ref_clk);
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ret = of_property_read_string(dev->of_node, "clock-output-names",
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&clk_init.name);
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if (ret < 0) {
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dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
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return ret;
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}
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hdmi_phy->dev = dev;
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hdmi_phy->conf =
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(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
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mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
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hdmi_phy->pll_hw.init = &clk_init;
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hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
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if (IS_ERR(hdmi_phy->pll)) {
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ret = PTR_ERR(hdmi_phy->pll);
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dev_err(dev, "Failed to register PLL: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
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&hdmi_phy->ibias);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
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&hdmi_phy->ibias_up);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
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return ret;
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}
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dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
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hdmi_phy->drv_imp_clk = 0x30;
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hdmi_phy->drv_imp_d2 = 0x30;
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hdmi_phy->drv_imp_d1 = 0x30;
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hdmi_phy->drv_imp_d0 = 0x30;
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phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
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if (IS_ERR(phy)) {
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dev_err(dev, "Failed to create HDMI PHY\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, hdmi_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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dev_err(dev, "Failed to register HDMI PHY\n");
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return PTR_ERR(phy_provider);
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}
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if (hdmi_phy->conf->pll_default_off)
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hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
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return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
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hdmi_phy->pll);
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}
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static const struct of_device_id mtk_hdmi_phy_match[] = {
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{ .compatible = "mediatek,mt2701-hdmi-phy",
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.data = &mtk_hdmi_phy_2701_conf,
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},
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{ .compatible = "mediatek,mt8173-hdmi-phy",
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.data = &mtk_hdmi_phy_8173_conf,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, mtk_hdmi_phy_match);
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static struct platform_driver mtk_hdmi_phy_driver = {
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.probe = mtk_hdmi_phy_probe,
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.driver = {
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.name = "mediatek-hdmi-phy",
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.of_match_table = mtk_hdmi_phy_match,
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},
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};
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module_platform_driver(mtk_hdmi_phy_driver);
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MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
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MODULE_LICENSE("GPL v2");
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