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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Andy Shevchenko](/assets/img/avatar_default.png)
GPIO library does copy the of_node from the parent device of the GPIO chip, there is no need to repeat this in the individual drivers. Remove these assignment all at once. For the details one may look into the of_gpio_dev_init() implementation. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211214125855.33207-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
923 lines
24 KiB
C
923 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014-2017 Broadcom
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*/
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/*
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* This file contains the Broadcom Iproc GPIO driver that supports 3
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* GPIO controllers on Iproc including the ASIU GPIO controller, the
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* chipCommonG GPIO controller, and the always-on GPIO controller. Basic
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* PINCONF such as bias pull up/down, and drive strength are also supported
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* in this driver.
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*
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* It provides the functionality where pins from the GPIO can be
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* individually muxed to GPIO function, if individual pad
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* configuration is supported, through the interaction with respective
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* SoCs IOMUX controller.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <linux/ioport.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "../pinctrl-utils.h"
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#define IPROC_GPIO_DATA_IN_OFFSET 0x00
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#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
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#define IPROC_GPIO_OUT_EN_OFFSET 0x08
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#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
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#define IPROC_GPIO_INT_DE_OFFSET 0x10
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#define IPROC_GPIO_INT_EDGE_OFFSET 0x14
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#define IPROC_GPIO_INT_MSK_OFFSET 0x18
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#define IPROC_GPIO_INT_STAT_OFFSET 0x1c
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#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
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#define IPROC_GPIO_INT_CLR_OFFSET 0x24
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#define IPROC_GPIO_PAD_RES_OFFSET 0x34
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#define IPROC_GPIO_RES_EN_OFFSET 0x38
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/* drive strength control for ASIU GPIO */
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#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
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/* pinconf for CCM GPIO */
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#define IPROC_GPIO_PULL_DN_OFFSET 0x10
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#define IPROC_GPIO_PULL_UP_OFFSET 0x14
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/* pinconf for CRMU(aon) GPIO and CCM GPIO*/
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#define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
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#define GPIO_BANK_SIZE 0x200
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#define NGPIOS_PER_BANK 32
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#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
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#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
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#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
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#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
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#define GPIO_DRV_STRENGTH_BITS 3
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#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
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enum iproc_pinconf_param {
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IPROC_PINCONF_DRIVE_STRENGTH = 0,
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IPROC_PINCONF_BIAS_DISABLE,
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IPROC_PINCONF_BIAS_PULL_UP,
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IPROC_PINCONF_BIAS_PULL_DOWN,
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IPROC_PINCON_MAX,
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};
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enum iproc_pinconf_ctrl_type {
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IOCTRL_TYPE_AON = 1,
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IOCTRL_TYPE_CDRU,
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IOCTRL_TYPE_INVALID,
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};
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/*
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* Iproc GPIO core
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*
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* @dev: pointer to device
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* @base: I/O register base for Iproc GPIO controller
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* @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
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* has the PINCONF support implemented outside of the GPIO block
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* @lock: lock to protect access to I/O registers
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* @gc: GPIO chip
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* @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
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* @pinmux_is_supported: flag to indicate this GPIO controller contains pins
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* that can be individually muxed to GPIO
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* @pinconf_disable: contains a list of PINCONF parameters that need to be
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* disabled
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* @nr_pinconf_disable: total number of PINCONF parameters that need to be
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* disabled
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* @pctl: pointer to pinctrl_dev
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* @pctldesc: pinctrl descriptor
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*/
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struct iproc_gpio {
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struct device *dev;
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void __iomem *base;
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void __iomem *io_ctrl;
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enum iproc_pinconf_ctrl_type io_ctrl_type;
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raw_spinlock_t lock;
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struct irq_chip irqchip;
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struct gpio_chip gc;
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unsigned num_banks;
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bool pinmux_is_supported;
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enum pin_config_param *pinconf_disable;
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unsigned int nr_pinconf_disable;
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctldesc;
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};
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/*
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* Mapping from PINCONF pins to GPIO pins is 1-to-1
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*/
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static inline unsigned iproc_pin_to_gpio(unsigned pin)
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{
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return pin;
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}
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/**
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* iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
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* Iproc GPIO register
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*
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* @chip: Iproc GPIO device
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* @reg: register offset
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* @gpio: GPIO pin
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* @set: set or clear
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*/
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static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
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unsigned gpio, bool set)
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{
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unsigned int offset = IPROC_GPIO_REG(gpio, reg);
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unsigned int shift = IPROC_GPIO_SHIFT(gpio);
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u32 val;
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val = readl(chip->base + offset);
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if (set)
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val |= BIT(shift);
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else
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val &= ~BIT(shift);
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writel(val, chip->base + offset);
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}
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static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
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unsigned gpio)
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{
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unsigned int offset = IPROC_GPIO_REG(gpio, reg);
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unsigned int shift = IPROC_GPIO_SHIFT(gpio);
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return !!(readl(chip->base + offset) & BIT(shift));
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}
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static void iproc_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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int i, bit;
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chained_irq_enter(irq_chip, desc);
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/* go through the entire GPIO banks and handle all interrupts */
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for (i = 0; i < chip->num_banks; i++) {
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unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
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IPROC_GPIO_INT_MSTAT_OFFSET);
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for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
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unsigned pin = NGPIOS_PER_BANK * i + bit;
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/*
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* Clear the interrupt before invoking the
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* handler, so we do not leave any window
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*/
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writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
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IPROC_GPIO_INT_CLR_OFFSET);
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generic_handle_domain_irq(gc->irq.domain, pin);
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}
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}
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chained_irq_exit(irq_chip, desc);
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}
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static void iproc_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = d->hwirq;
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unsigned int offset = IPROC_GPIO_REG(gpio,
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IPROC_GPIO_INT_CLR_OFFSET);
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unsigned int shift = IPROC_GPIO_SHIFT(gpio);
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u32 val = BIT(shift);
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writel(val, chip->base + offset);
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}
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/**
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* iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
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*
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* @d: IRQ chip data
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* @unmask: mask/unmask GPIO interrupt
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*/
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static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = d->hwirq;
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iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
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}
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static void iproc_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_gpio_irq_set_mask(d, false);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void iproc_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_gpio_irq_set_mask(d, true);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = d->hwirq;
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bool level_triggered = false;
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bool dual_edge = false;
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bool rising_or_high = false;
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unsigned long flags;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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rising_or_high = true;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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break;
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case IRQ_TYPE_EDGE_BOTH:
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dual_edge = true;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level_triggered = true;
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rising_or_high = true;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level_triggered = true;
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break;
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default:
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dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
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type);
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
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level_triggered);
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iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
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iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
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rising_or_high);
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev,
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"gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
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gpio, level_triggered, dual_edge, rising_or_high);
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return 0;
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}
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/*
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* Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
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*/
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static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = gc->base + offset;
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/* not all Iproc GPIO pins can be muxed individually */
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if (!chip->pinmux_is_supported)
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return 0;
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return pinctrl_gpio_request(gpio);
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}
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static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned gpio = gc->base + offset;
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if (!chip->pinmux_is_supported)
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return;
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pinctrl_gpio_free(gpio);
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}
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static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
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return 0;
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}
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static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
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int val)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
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iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
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return 0;
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}
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static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
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unsigned int shift = IPROC_GPIO_SHIFT(gpio);
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if (readl(chip->base + offset) & BIT(shift))
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&chip->lock, flags);
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iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
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}
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static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
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{
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struct iproc_gpio *chip = gpiochip_get_data(gc);
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unsigned int offset = IPROC_GPIO_REG(gpio,
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IPROC_GPIO_DATA_IN_OFFSET);
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unsigned int shift = IPROC_GPIO_SHIFT(gpio);
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return !!(readl(chip->base + offset) & BIT(shift));
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}
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/*
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* Mapping of the iProc PINCONF parameters to the generic pin configuration
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* parameters
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*/
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static const enum pin_config_param iproc_pinconf_disable_map[] = {
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[IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
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[IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
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[IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
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[IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
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};
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static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
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enum pin_config_param param)
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{
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unsigned int i;
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if (!chip->nr_pinconf_disable)
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return false;
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for (i = 0; i < chip->nr_pinconf_disable; i++)
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if (chip->pinconf_disable[i] == param)
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return true;
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return false;
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}
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static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
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unsigned long disable_mask)
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{
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unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
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unsigned int bit, nbits = 0;
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/* figure out total number of PINCONF parameters to disable */
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for_each_set_bit(bit, &disable_mask, map_size)
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nbits++;
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if (!nbits)
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return 0;
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/*
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* Allocate an array to store PINCONF parameters that need to be
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* disabled
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*/
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chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
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sizeof(*chip->pinconf_disable),
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GFP_KERNEL);
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if (!chip->pinconf_disable)
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return -ENOMEM;
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chip->nr_pinconf_disable = nbits;
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/* now store these parameters */
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nbits = 0;
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for_each_set_bit(bit, &disable_mask, map_size)
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chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
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return 0;
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}
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static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return 1;
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}
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/*
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* Only one group: "gpio_grp", since this local pinctrl device only performs
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* GPIO specific PINCONF configurations
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*/
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static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return "gpio_grp";
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}
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static const struct pinctrl_ops iproc_pctrl_ops = {
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.get_groups_count = iproc_get_groups_count,
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.get_group_name = iproc_get_group_name,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
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bool disable, bool pull_up)
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{
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void __iomem *base;
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unsigned long flags;
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unsigned int shift;
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u32 val_1, val_2;
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raw_spin_lock_irqsave(&chip->lock, flags);
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if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
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base = chip->io_ctrl;
|
|
shift = IPROC_GPIO_SHIFT(gpio);
|
|
|
|
val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
|
|
val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
|
|
if (disable) {
|
|
/* no pull-up or pull-down */
|
|
val_1 &= ~BIT(shift);
|
|
val_2 &= ~BIT(shift);
|
|
} else if (pull_up) {
|
|
val_1 |= BIT(shift);
|
|
val_2 &= ~BIT(shift);
|
|
} else {
|
|
val_1 &= ~BIT(shift);
|
|
val_2 |= BIT(shift);
|
|
}
|
|
writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
|
|
writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
|
|
} else {
|
|
if (disable) {
|
|
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
|
|
false);
|
|
} else {
|
|
iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
|
|
pull_up);
|
|
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
|
|
true);
|
|
}
|
|
}
|
|
|
|
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
|
dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
|
|
bool *disable, bool *pull_up)
|
|
{
|
|
void __iomem *base;
|
|
unsigned long flags;
|
|
unsigned int shift;
|
|
u32 val_1, val_2;
|
|
|
|
raw_spin_lock_irqsave(&chip->lock, flags);
|
|
if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
|
|
base = chip->io_ctrl;
|
|
shift = IPROC_GPIO_SHIFT(gpio);
|
|
|
|
val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
|
|
val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
|
|
|
|
*pull_up = val_1 ? true : false;
|
|
*disable = (val_1 | val_2) ? false : true;
|
|
|
|
} else {
|
|
*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
|
|
*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
|
|
}
|
|
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
|
}
|
|
|
|
#define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
|
|
((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
|
|
((type) == IOCTRL_TYPE_CDRU) ? \
|
|
((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
|
|
((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
|
|
|
|
static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
|
|
unsigned strength)
|
|
{
|
|
void __iomem *base;
|
|
unsigned int i, offset, shift;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
/* make sure drive strength is supported */
|
|
if (strength < 2 || strength > 16 || (strength % 2))
|
|
return -ENOTSUPP;
|
|
|
|
if (chip->io_ctrl) {
|
|
base = chip->io_ctrl;
|
|
} else {
|
|
base = chip->base;
|
|
}
|
|
|
|
shift = IPROC_GPIO_SHIFT(gpio);
|
|
|
|
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
|
|
strength);
|
|
|
|
raw_spin_lock_irqsave(&chip->lock, flags);
|
|
strength = (strength / 2) - 1;
|
|
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
|
|
offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
|
|
val = readl(base + offset);
|
|
val &= ~BIT(shift);
|
|
val |= ((strength >> i) & 0x1) << shift;
|
|
writel(val, base + offset);
|
|
}
|
|
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
|
|
u16 *strength)
|
|
{
|
|
void __iomem *base;
|
|
unsigned int i, offset, shift;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
if (chip->io_ctrl) {
|
|
base = chip->io_ctrl;
|
|
} else {
|
|
base = chip->base;
|
|
}
|
|
|
|
shift = IPROC_GPIO_SHIFT(gpio);
|
|
|
|
raw_spin_lock_irqsave(&chip->lock, flags);
|
|
*strength = 0;
|
|
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
|
|
offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
|
|
val = readl(base + offset) & BIT(shift);
|
|
val >>= shift;
|
|
*strength += (val << i);
|
|
}
|
|
|
|
/* convert to mA */
|
|
*strength = (*strength + 1) * 2;
|
|
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
|
|
unsigned long *config)
|
|
{
|
|
struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
|
enum pin_config_param param = pinconf_to_config_param(*config);
|
|
unsigned gpio = iproc_pin_to_gpio(pin);
|
|
u16 arg;
|
|
bool disable, pull_up;
|
|
int ret;
|
|
|
|
if (iproc_pinconf_param_is_disabled(chip, param))
|
|
return -ENOTSUPP;
|
|
|
|
switch (param) {
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
|
|
if (disable)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
|
|
if (!disable && pull_up)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
|
|
if (!disable && !pull_up)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
ret = iproc_gpio_get_strength(chip, gpio, &arg);
|
|
if (ret)
|
|
return ret;
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
|
|
unsigned long *configs, unsigned num_configs)
|
|
{
|
|
struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
|
enum pin_config_param param;
|
|
u32 arg;
|
|
unsigned i, gpio = iproc_pin_to_gpio(pin);
|
|
int ret = -ENOTSUPP;
|
|
|
|
for (i = 0; i < num_configs; i++) {
|
|
param = pinconf_to_config_param(configs[i]);
|
|
|
|
if (iproc_pinconf_param_is_disabled(chip, param))
|
|
return -ENOTSUPP;
|
|
|
|
arg = pinconf_to_config_argument(configs[i]);
|
|
|
|
switch (param) {
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
ret = iproc_gpio_set_pull(chip, gpio, true, false);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
ret = iproc_gpio_set_pull(chip, gpio, false, true);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
ret = iproc_gpio_set_pull(chip, gpio, false, false);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
ret = iproc_gpio_set_strength(chip, gpio, arg);
|
|
if (ret < 0)
|
|
goto out;
|
|
break;
|
|
|
|
default:
|
|
dev_err(chip->dev, "invalid configuration\n");
|
|
return -ENOTSUPP;
|
|
}
|
|
} /* for each config */
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static const struct pinconf_ops iproc_pconf_ops = {
|
|
.is_generic = true,
|
|
.pin_config_get = iproc_pin_config_get,
|
|
.pin_config_set = iproc_pin_config_set,
|
|
};
|
|
|
|
/*
|
|
* Iproc GPIO controller supports some PINCONF related configurations such as
|
|
* pull up, pull down, and drive strength, when the pin is configured to GPIO
|
|
*
|
|
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
|
|
* local GPIO pins
|
|
*/
|
|
static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
|
|
{
|
|
struct pinctrl_desc *pctldesc = &chip->pctldesc;
|
|
struct pinctrl_pin_desc *pins;
|
|
struct gpio_chip *gc = &chip->gc;
|
|
int i;
|
|
|
|
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < gc->ngpio; i++) {
|
|
pins[i].number = i;
|
|
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
|
|
"gpio-%d", i);
|
|
if (!pins[i].name)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pctldesc->name = dev_name(chip->dev);
|
|
pctldesc->pctlops = &iproc_pctrl_ops;
|
|
pctldesc->pins = pins;
|
|
pctldesc->npins = gc->ngpio;
|
|
pctldesc->confops = &iproc_pconf_ops;
|
|
|
|
chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
|
|
if (IS_ERR(chip->pctl)) {
|
|
dev_err(chip->dev, "unable to register pinctrl device\n");
|
|
return PTR_ERR(chip->pctl);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id iproc_gpio_of_match[] = {
|
|
{ .compatible = "brcm,iproc-gpio" },
|
|
{ .compatible = "brcm,cygnus-ccm-gpio" },
|
|
{ .compatible = "brcm,cygnus-asiu-gpio" },
|
|
{ .compatible = "brcm,cygnus-crmu-gpio" },
|
|
{ .compatible = "brcm,iproc-nsp-gpio" },
|
|
{ .compatible = "brcm,iproc-stingray-gpio" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int iproc_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
struct iproc_gpio *chip;
|
|
struct gpio_chip *gc;
|
|
u32 ngpios, pinconf_disable_mask = 0;
|
|
int irq, ret;
|
|
bool no_pinconf = false;
|
|
enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
|
|
|
|
/* NSP does not support drive strength config */
|
|
if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
|
|
pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
|
|
/* Stingray does not support pinconf in this controller */
|
|
else if (of_device_is_compatible(dev->of_node,
|
|
"brcm,iproc-stingray-gpio"))
|
|
no_pinconf = true;
|
|
|
|
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
|
|
chip->dev = dev;
|
|
platform_set_drvdata(pdev, chip);
|
|
|
|
chip->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(chip->base)) {
|
|
dev_err(dev, "unable to map I/O memory\n");
|
|
return PTR_ERR(chip->base);
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (res) {
|
|
chip->io_ctrl = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(chip->io_ctrl))
|
|
return PTR_ERR(chip->io_ctrl);
|
|
if (of_device_is_compatible(dev->of_node,
|
|
"brcm,cygnus-ccm-gpio"))
|
|
io_ctrl_type = IOCTRL_TYPE_CDRU;
|
|
else
|
|
io_ctrl_type = IOCTRL_TYPE_AON;
|
|
}
|
|
|
|
chip->io_ctrl_type = io_ctrl_type;
|
|
|
|
if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
|
|
dev_err(&pdev->dev, "missing ngpios DT property\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
raw_spin_lock_init(&chip->lock);
|
|
|
|
gc = &chip->gc;
|
|
gc->base = -1;
|
|
gc->ngpio = ngpios;
|
|
chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
|
|
gc->label = dev_name(dev);
|
|
gc->parent = dev;
|
|
gc->request = iproc_gpio_request;
|
|
gc->free = iproc_gpio_free;
|
|
gc->direction_input = iproc_gpio_direction_input;
|
|
gc->direction_output = iproc_gpio_direction_output;
|
|
gc->get_direction = iproc_gpio_get_direction;
|
|
gc->set = iproc_gpio_set;
|
|
gc->get = iproc_gpio_get;
|
|
|
|
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
|
|
"gpio-ranges");
|
|
|
|
/* optional GPIO interrupt support */
|
|
irq = platform_get_irq_optional(pdev, 0);
|
|
if (irq > 0) {
|
|
struct irq_chip *irqc;
|
|
struct gpio_irq_chip *girq;
|
|
|
|
irqc = &chip->irqchip;
|
|
irqc->name = dev_name(dev);
|
|
irqc->irq_ack = iproc_gpio_irq_ack;
|
|
irqc->irq_mask = iproc_gpio_irq_mask;
|
|
irqc->irq_unmask = iproc_gpio_irq_unmask;
|
|
irqc->irq_set_type = iproc_gpio_irq_set_type;
|
|
irqc->irq_enable = iproc_gpio_irq_unmask;
|
|
irqc->irq_disable = iproc_gpio_irq_mask;
|
|
|
|
girq = &gc->irq;
|
|
girq->chip = irqc;
|
|
girq->parent_handler = iproc_gpio_irq_handler;
|
|
girq->num_parents = 1;
|
|
girq->parents = devm_kcalloc(dev, 1,
|
|
sizeof(*girq->parents),
|
|
GFP_KERNEL);
|
|
if (!girq->parents)
|
|
return -ENOMEM;
|
|
girq->parents[0] = irq;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_bad_irq;
|
|
}
|
|
|
|
ret = gpiochip_add_data(gc, chip);
|
|
if (ret < 0) {
|
|
dev_err(dev, "unable to add GPIO chip\n");
|
|
return ret;
|
|
}
|
|
|
|
if (!no_pinconf) {
|
|
ret = iproc_gpio_register_pinconf(chip);
|
|
if (ret) {
|
|
dev_err(dev, "unable to register pinconf\n");
|
|
goto err_rm_gpiochip;
|
|
}
|
|
|
|
if (pinconf_disable_mask) {
|
|
ret = iproc_pinconf_disable_map_create(chip,
|
|
pinconf_disable_mask);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"unable to create pinconf disable map\n");
|
|
goto err_rm_gpiochip;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_rm_gpiochip:
|
|
gpiochip_remove(gc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver iproc_gpio_driver = {
|
|
.driver = {
|
|
.name = "iproc-gpio",
|
|
.of_match_table = iproc_gpio_of_match,
|
|
},
|
|
.probe = iproc_gpio_probe,
|
|
};
|
|
|
|
static int __init iproc_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&iproc_gpio_driver);
|
|
}
|
|
arch_initcall_sync(iproc_gpio_init);
|