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7558f978f9
Tegra SPI controller has TX and RX trimmers to tuning the delay of SPI master clock with respect to the data. TX and RX tap values are based on the platform validation across the PVT and the trimmer values vary based on the trace lengths to the corresponding SPI devices. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org> |
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| .. | ||
| bindings | ||
| booting-without-of.txt | ||
| changesets.txt | ||
| dynamic-resolution-notes.txt | ||
| of_unittest.txt | ||
| overlay-notes.txt | ||
| usage-model.txt | ||
| writing-schema.md | ||