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75ded18a5e
Add LSX and LASX implementations of xor operations, operating on 64 bytes (one L1 cache line) at a time, for a balance between memory utilization and instruction mix. Huacai confirmed that all future LoongArch implementations by Loongson (that we care) will likely also feature 64-byte cache lines, and experiments show no throughput improvement with further unrolling. Performance numbers measured during system boot on a 3A5000 @ 2.5GHz: > 8regs : 12702 MB/sec > 8regs_prefetch : 10920 MB/sec > 32regs : 12686 MB/sec > 32regs_prefetch : 10918 MB/sec > lsx : 17589 MB/sec > lasx : 26116 MB/sec Acked-by: Song Liu <song@kernel.org> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
11 lines
310 B
Makefile
11 lines
310 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for LoongArch-specific library files.
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#
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lib-y += delay.o memset.o memcpy.o memmove.o \
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clear_user.o copy_user.o csum.o dump_tlb.o unaligned.o
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obj-$(CONFIG_CPU_HAS_LSX) += xor_simd.o xor_simd_glue.o
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obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
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