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ae832e329a
Add HMAC support to the Keem Bay OCS HCU driver, thus making it provide the following additional transformations: - hmac(sha256) - hmac(sha384) - hmac(sha512) - hmac(sm3) The Keem Bay OCS HCU hardware does not allow "context-switch" for HMAC operations, i.e., it does not support computing a partial HMAC, save its state and then continue it later. Therefore, full hardware acceleration is provided only when possible (e.g., when crypto_ahash_digest() is called); in all other cases hardware acceleration is only partial (OPAD and IPAD calculation is done in software, while hashing is hardware accelerated). Co-developed-by: Declan Murphy <declan.murphy@intel.com> Signed-off-by: Declan Murphy <declan.murphy@intel.com> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Keem Bay OCS HCU Crypto Driver.
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*
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* Copyright (C) 2018-2020 Intel Corporation
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*/
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#include <linux/dma-mapping.h>
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#ifndef _CRYPTO_OCS_HCU_H
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#define _CRYPTO_OCS_HCU_H
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#define OCS_HCU_DMA_BIT_MASK DMA_BIT_MASK(32)
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#define OCS_HCU_HW_KEY_LEN 64
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struct ocs_hcu_dma_list;
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enum ocs_hcu_algo {
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OCS_HCU_ALGO_SHA256 = 2,
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OCS_HCU_ALGO_SHA224 = 3,
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OCS_HCU_ALGO_SHA384 = 4,
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OCS_HCU_ALGO_SHA512 = 5,
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OCS_HCU_ALGO_SM3 = 6,
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};
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/**
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* struct ocs_hcu_dev - OCS HCU device context.
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* @list: List of device contexts.
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* @dev: OCS HCU device.
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* @io_base: Base address of OCS HCU registers.
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* @engine: Crypto engine for the device.
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* @irq: IRQ number.
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* @irq_done: Completion for IRQ.
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* @irq_err: Flag indicating an IRQ error has happened.
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*/
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struct ocs_hcu_dev {
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struct list_head list;
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struct device *dev;
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void __iomem *io_base;
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struct crypto_engine *engine;
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int irq;
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struct completion irq_done;
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bool irq_err;
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};
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/**
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* struct ocs_hcu_idata - Intermediate data generated by the HCU.
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* @msg_len_lo: Length of data the HCU has operated on in bits, low 32b.
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* @msg_len_hi: Length of data the HCU has operated on in bits, high 32b.
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* @digest: The digest read from the HCU. If the HCU is terminated, it will
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* contain the actual hash digest. Otherwise it is the intermediate
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* state.
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*/
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struct ocs_hcu_idata {
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u32 msg_len_lo;
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u32 msg_len_hi;
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u8 digest[SHA512_DIGEST_SIZE];
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};
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/**
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* struct ocs_hcu_hash_ctx - Context for OCS HCU hashing operation.
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* @algo: The hashing algorithm being used.
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* @idata: The current intermediate data.
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*/
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struct ocs_hcu_hash_ctx {
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enum ocs_hcu_algo algo;
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struct ocs_hcu_idata idata;
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};
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irqreturn_t ocs_hcu_irq_handler(int irq, void *dev_id);
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struct ocs_hcu_dma_list *ocs_hcu_dma_list_alloc(struct ocs_hcu_dev *hcu_dev,
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int max_nents);
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void ocs_hcu_dma_list_free(struct ocs_hcu_dev *hcu_dev,
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struct ocs_hcu_dma_list *dma_list);
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int ocs_hcu_dma_list_add_tail(struct ocs_hcu_dev *hcu_dev,
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struct ocs_hcu_dma_list *dma_list,
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dma_addr_t addr, u32 len);
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int ocs_hcu_hash_init(struct ocs_hcu_hash_ctx *ctx, enum ocs_hcu_algo algo);
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int ocs_hcu_hash_update(struct ocs_hcu_dev *hcu_dev,
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struct ocs_hcu_hash_ctx *ctx,
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const struct ocs_hcu_dma_list *dma_list);
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int ocs_hcu_hash_finup(struct ocs_hcu_dev *hcu_dev,
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const struct ocs_hcu_hash_ctx *ctx,
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const struct ocs_hcu_dma_list *dma_list,
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u8 *dgst, size_t dgst_len);
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int ocs_hcu_hash_final(struct ocs_hcu_dev *hcu_dev,
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const struct ocs_hcu_hash_ctx *ctx, u8 *dgst,
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size_t dgst_len);
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int ocs_hcu_digest(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
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void *data, size_t data_len, u8 *dgst, size_t dgst_len);
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int ocs_hcu_hmac(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
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const u8 *key, size_t key_len,
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const struct ocs_hcu_dma_list *dma_list,
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u8 *dgst, size_t dgst_len);
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#endif /* _CRYPTO_OCS_HCU_H */
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