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![Vinod Koul](/assets/img/avatar_default.png)
This driver when compiled on 64 bits gave warnings: drivers/dma/sa11x0-dma.c:602:2: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 6 has type ‘size_t’ [-Wformat=] We should use %zu to print 'size_t' values. Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
1106 lines
27 KiB
C
1106 lines
27 KiB
C
/*
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* SA11x0 DMAengine support
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*
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* Copyright (C) 2012 Russell King
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* Derived in part from arch/arm/mach-sa1100/dma.c,
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* Copyright (C) 2000, 2001 by Nicolas Pitre
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sa11x0-dma.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "virt-dma.h"
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#define NR_PHY_CHAN 6
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#define DMA_ALIGN 3
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#define DMA_MAX_SIZE 0x1fff
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#define DMA_CHUNK_SIZE 0x1000
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#define DMA_DDAR 0x00
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#define DMA_DCSR_S 0x04
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#define DMA_DCSR_C 0x08
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#define DMA_DCSR_R 0x0c
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#define DMA_DBSA 0x10
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#define DMA_DBTA 0x14
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#define DMA_DBSB 0x18
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#define DMA_DBTB 0x1c
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#define DMA_SIZE 0x20
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#define DCSR_RUN (1 << 0)
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#define DCSR_IE (1 << 1)
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#define DCSR_ERROR (1 << 2)
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#define DCSR_DONEA (1 << 3)
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#define DCSR_STRTA (1 << 4)
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#define DCSR_DONEB (1 << 5)
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#define DCSR_STRTB (1 << 6)
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#define DCSR_BIU (1 << 7)
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#define DDAR_RW (1 << 0) /* 0 = W, 1 = R */
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#define DDAR_E (1 << 1) /* 0 = LE, 1 = BE */
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#define DDAR_BS (1 << 2) /* 0 = BS4, 1 = BS8 */
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#define DDAR_DW (1 << 3) /* 0 = 8b, 1 = 16b */
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#define DDAR_Ser0UDCTr (0x0 << 4)
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#define DDAR_Ser0UDCRc (0x1 << 4)
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#define DDAR_Ser1SDLCTr (0x2 << 4)
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#define DDAR_Ser1SDLCRc (0x3 << 4)
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#define DDAR_Ser1UARTTr (0x4 << 4)
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#define DDAR_Ser1UARTRc (0x5 << 4)
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#define DDAR_Ser2ICPTr (0x6 << 4)
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#define DDAR_Ser2ICPRc (0x7 << 4)
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#define DDAR_Ser3UARTTr (0x8 << 4)
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#define DDAR_Ser3UARTRc (0x9 << 4)
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#define DDAR_Ser4MCP0Tr (0xa << 4)
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#define DDAR_Ser4MCP0Rc (0xb << 4)
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#define DDAR_Ser4MCP1Tr (0xc << 4)
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#define DDAR_Ser4MCP1Rc (0xd << 4)
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#define DDAR_Ser4SSPTr (0xe << 4)
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#define DDAR_Ser4SSPRc (0xf << 4)
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struct sa11x0_dma_sg {
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u32 addr;
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u32 len;
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};
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struct sa11x0_dma_desc {
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struct virt_dma_desc vd;
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u32 ddar;
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size_t size;
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unsigned period;
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bool cyclic;
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unsigned sglen;
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struct sa11x0_dma_sg sg[0];
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};
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struct sa11x0_dma_phy;
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struct sa11x0_dma_chan {
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struct virt_dma_chan vc;
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/* protected by c->vc.lock */
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struct sa11x0_dma_phy *phy;
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enum dma_status status;
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/* protected by d->lock */
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struct list_head node;
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u32 ddar;
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const char *name;
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};
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struct sa11x0_dma_phy {
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void __iomem *base;
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struct sa11x0_dma_dev *dev;
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unsigned num;
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struct sa11x0_dma_chan *vchan;
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/* Protected by c->vc.lock */
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unsigned sg_load;
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struct sa11x0_dma_desc *txd_load;
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unsigned sg_done;
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struct sa11x0_dma_desc *txd_done;
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u32 dbs[2];
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u32 dbt[2];
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u32 dcsr;
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};
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struct sa11x0_dma_dev {
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struct dma_device slave;
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void __iomem *base;
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spinlock_t lock;
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struct tasklet_struct task;
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struct list_head chan_pending;
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struct sa11x0_dma_phy phy[NR_PHY_CHAN];
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};
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static struct sa11x0_dma_chan *to_sa11x0_dma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct sa11x0_dma_chan, vc.chan);
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}
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static struct sa11x0_dma_dev *to_sa11x0_dma(struct dma_device *dmadev)
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{
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return container_of(dmadev, struct sa11x0_dma_dev, slave);
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}
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static struct sa11x0_dma_desc *sa11x0_dma_next_desc(struct sa11x0_dma_chan *c)
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{
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struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
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return vd ? container_of(vd, struct sa11x0_dma_desc, vd) : NULL;
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}
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static void sa11x0_dma_free_desc(struct virt_dma_desc *vd)
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{
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kfree(container_of(vd, struct sa11x0_dma_desc, vd));
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}
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static void sa11x0_dma_start_desc(struct sa11x0_dma_phy *p, struct sa11x0_dma_desc *txd)
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{
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list_del(&txd->vd.node);
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p->txd_load = txd;
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p->sg_load = 0;
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dev_vdbg(p->dev->slave.dev, "pchan %u: txd %p[%x]: starting: DDAR:%x\n",
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p->num, &txd->vd, txd->vd.tx.cookie, txd->ddar);
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}
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static void noinline sa11x0_dma_start_sg(struct sa11x0_dma_phy *p,
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struct sa11x0_dma_chan *c)
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{
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struct sa11x0_dma_desc *txd = p->txd_load;
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struct sa11x0_dma_sg *sg;
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void __iomem *base = p->base;
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unsigned dbsx, dbtx;
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u32 dcsr;
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if (!txd)
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return;
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dcsr = readl_relaxed(base + DMA_DCSR_R);
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/* Don't try to load the next transfer if both buffers are started */
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if ((dcsr & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB))
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return;
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if (p->sg_load == txd->sglen) {
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if (!txd->cyclic) {
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struct sa11x0_dma_desc *txn = sa11x0_dma_next_desc(c);
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/*
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* We have reached the end of the current descriptor.
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* Peek at the next descriptor, and if compatible with
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* the current, start processing it.
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*/
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if (txn && txn->ddar == txd->ddar) {
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txd = txn;
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sa11x0_dma_start_desc(p, txn);
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} else {
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p->txd_load = NULL;
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return;
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}
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} else {
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/* Cyclic: reset back to beginning */
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p->sg_load = 0;
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}
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}
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sg = &txd->sg[p->sg_load++];
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/* Select buffer to load according to channel status */
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if (((dcsr & (DCSR_BIU | DCSR_STRTB)) == (DCSR_BIU | DCSR_STRTB)) ||
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((dcsr & (DCSR_BIU | DCSR_STRTA)) == 0)) {
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dbsx = DMA_DBSA;
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dbtx = DMA_DBTA;
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dcsr = DCSR_STRTA | DCSR_IE | DCSR_RUN;
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} else {
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dbsx = DMA_DBSB;
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dbtx = DMA_DBTB;
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dcsr = DCSR_STRTB | DCSR_IE | DCSR_RUN;
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}
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writel_relaxed(sg->addr, base + dbsx);
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writel_relaxed(sg->len, base + dbtx);
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writel(dcsr, base + DMA_DCSR_S);
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dev_dbg(p->dev->slave.dev, "pchan %u: load: DCSR:%02x DBS%c:%08x DBT%c:%08x\n",
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p->num, dcsr,
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'A' + (dbsx == DMA_DBSB), sg->addr,
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'A' + (dbtx == DMA_DBTB), sg->len);
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}
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static void noinline sa11x0_dma_complete(struct sa11x0_dma_phy *p,
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struct sa11x0_dma_chan *c)
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{
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struct sa11x0_dma_desc *txd = p->txd_done;
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if (++p->sg_done == txd->sglen) {
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if (!txd->cyclic) {
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vchan_cookie_complete(&txd->vd);
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p->sg_done = 0;
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p->txd_done = p->txd_load;
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if (!p->txd_done)
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tasklet_schedule(&p->dev->task);
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} else {
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if ((p->sg_done % txd->period) == 0)
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vchan_cyclic_callback(&txd->vd);
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/* Cyclic: reset back to beginning */
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p->sg_done = 0;
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}
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}
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sa11x0_dma_start_sg(p, c);
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}
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static irqreturn_t sa11x0_dma_irq(int irq, void *dev_id)
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{
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struct sa11x0_dma_phy *p = dev_id;
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struct sa11x0_dma_dev *d = p->dev;
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struct sa11x0_dma_chan *c;
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u32 dcsr;
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dcsr = readl_relaxed(p->base + DMA_DCSR_R);
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if (!(dcsr & (DCSR_ERROR | DCSR_DONEA | DCSR_DONEB)))
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return IRQ_NONE;
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/* Clear reported status bits */
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writel_relaxed(dcsr & (DCSR_ERROR | DCSR_DONEA | DCSR_DONEB),
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p->base + DMA_DCSR_C);
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dev_dbg(d->slave.dev, "pchan %u: irq: DCSR:%02x\n", p->num, dcsr);
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if (dcsr & DCSR_ERROR) {
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dev_err(d->slave.dev, "pchan %u: error. DCSR:%02x DDAR:%08x DBSA:%08x DBTA:%08x DBSB:%08x DBTB:%08x\n",
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p->num, dcsr,
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readl_relaxed(p->base + DMA_DDAR),
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readl_relaxed(p->base + DMA_DBSA),
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readl_relaxed(p->base + DMA_DBTA),
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readl_relaxed(p->base + DMA_DBSB),
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readl_relaxed(p->base + DMA_DBTB));
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}
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c = p->vchan;
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if (c) {
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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/*
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* Now that we're holding the lock, check that the vchan
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* really is associated with this pchan before touching the
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* hardware. This should always succeed, because we won't
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* change p->vchan or c->phy while the channel is actively
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* transferring.
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*/
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if (c->phy == p) {
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if (dcsr & DCSR_DONEA)
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sa11x0_dma_complete(p, c);
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if (dcsr & DCSR_DONEB)
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sa11x0_dma_complete(p, c);
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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return IRQ_HANDLED;
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}
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static void sa11x0_dma_start_txd(struct sa11x0_dma_chan *c)
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{
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struct sa11x0_dma_desc *txd = sa11x0_dma_next_desc(c);
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/* If the issued list is empty, we have no further txds to process */
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if (txd) {
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struct sa11x0_dma_phy *p = c->phy;
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sa11x0_dma_start_desc(p, txd);
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p->txd_done = txd;
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p->sg_done = 0;
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/* The channel should not have any transfers started */
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WARN_ON(readl_relaxed(p->base + DMA_DCSR_R) &
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(DCSR_STRTA | DCSR_STRTB));
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/* Clear the run and start bits before changing DDAR */
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writel_relaxed(DCSR_RUN | DCSR_STRTA | DCSR_STRTB,
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p->base + DMA_DCSR_C);
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writel_relaxed(txd->ddar, p->base + DMA_DDAR);
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/* Try to start both buffers */
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sa11x0_dma_start_sg(p, c);
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sa11x0_dma_start_sg(p, c);
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}
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}
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static void sa11x0_dma_tasklet(unsigned long arg)
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{
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struct sa11x0_dma_dev *d = (struct sa11x0_dma_dev *)arg;
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struct sa11x0_dma_phy *p;
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struct sa11x0_dma_chan *c;
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unsigned pch, pch_alloc = 0;
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dev_dbg(d->slave.dev, "tasklet enter\n");
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list_for_each_entry(c, &d->slave.channels, vc.chan.device_node) {
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spin_lock_irq(&c->vc.lock);
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p = c->phy;
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if (p && !p->txd_done) {
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sa11x0_dma_start_txd(c);
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if (!p->txd_done) {
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/* No current txd associated with this channel */
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dev_dbg(d->slave.dev, "pchan %u: free\n", p->num);
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/* Mark this channel free */
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c->phy = NULL;
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p->vchan = NULL;
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}
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}
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spin_unlock_irq(&c->vc.lock);
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}
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spin_lock_irq(&d->lock);
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for (pch = 0; pch < NR_PHY_CHAN; pch++) {
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p = &d->phy[pch];
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if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
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c = list_first_entry(&d->chan_pending,
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struct sa11x0_dma_chan, node);
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list_del_init(&c->node);
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pch_alloc |= 1 << pch;
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/* Mark this channel allocated */
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p->vchan = c;
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dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
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}
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}
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spin_unlock_irq(&d->lock);
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for (pch = 0; pch < NR_PHY_CHAN; pch++) {
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if (pch_alloc & (1 << pch)) {
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p = &d->phy[pch];
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c = p->vchan;
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spin_lock_irq(&c->vc.lock);
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c->phy = p;
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sa11x0_dma_start_txd(c);
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spin_unlock_irq(&c->vc.lock);
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}
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}
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dev_dbg(d->slave.dev, "tasklet exit\n");
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}
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static void sa11x0_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
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struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
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unsigned long flags;
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spin_lock_irqsave(&d->lock, flags);
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list_del_init(&c->node);
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spin_unlock_irqrestore(&d->lock, flags);
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vchan_free_chan_resources(&c->vc);
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}
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static dma_addr_t sa11x0_dma_pos(struct sa11x0_dma_phy *p)
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{
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unsigned reg;
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u32 dcsr;
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dcsr = readl_relaxed(p->base + DMA_DCSR_R);
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if ((dcsr & (DCSR_BIU | DCSR_STRTA)) == DCSR_STRTA ||
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(dcsr & (DCSR_BIU | DCSR_STRTB)) == DCSR_BIU)
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reg = DMA_DBSA;
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else
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reg = DMA_DBSB;
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return readl_relaxed(p->base + reg);
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}
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static enum dma_status sa11x0_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *state)
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{
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struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
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struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
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struct sa11x0_dma_phy *p;
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struct virt_dma_desc *vd;
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unsigned long flags;
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enum dma_status ret;
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ret = dma_cookie_status(&c->vc.chan, cookie, state);
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if (ret == DMA_COMPLETE)
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return ret;
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if (!state)
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return c->status;
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spin_lock_irqsave(&c->vc.lock, flags);
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p = c->phy;
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/*
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* If the cookie is on our issue queue, then the residue is
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* its total size.
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*/
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vd = vchan_find_desc(&c->vc, cookie);
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if (vd) {
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state->residue = container_of(vd, struct sa11x0_dma_desc, vd)->size;
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} else if (!p) {
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state->residue = 0;
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} else {
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struct sa11x0_dma_desc *txd;
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size_t bytes = 0;
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if (p->txd_done && p->txd_done->vd.tx.cookie == cookie)
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txd = p->txd_done;
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else if (p->txd_load && p->txd_load->vd.tx.cookie == cookie)
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txd = p->txd_load;
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else
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txd = NULL;
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ret = c->status;
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if (txd) {
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dma_addr_t addr = sa11x0_dma_pos(p);
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unsigned i;
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|
|
dev_vdbg(d->slave.dev, "tx_status: addr:%pad\n", &addr);
|
|
|
|
for (i = 0; i < txd->sglen; i++) {
|
|
dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x\n",
|
|
i, txd->sg[i].addr, txd->sg[i].len);
|
|
if (addr >= txd->sg[i].addr &&
|
|
addr < txd->sg[i].addr + txd->sg[i].len) {
|
|
unsigned len;
|
|
|
|
len = txd->sg[i].len -
|
|
(addr - txd->sg[i].addr);
|
|
dev_vdbg(d->slave.dev, "tx_status: [%u] +%x\n",
|
|
i, len);
|
|
bytes += len;
|
|
i++;
|
|
break;
|
|
}
|
|
}
|
|
for (; i < txd->sglen; i++) {
|
|
dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x ++\n",
|
|
i, txd->sg[i].addr, txd->sg[i].len);
|
|
bytes += txd->sg[i].len;
|
|
}
|
|
}
|
|
state->residue = bytes;
|
|
}
|
|
spin_unlock_irqrestore(&c->vc.lock, flags);
|
|
|
|
dev_vdbg(d->slave.dev, "tx_status: bytes 0x%x\n", state->residue);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Move pending txds to the issued list, and re-init pending list.
|
|
* If not already pending, add this channel to the list of pending
|
|
* channels and trigger the tasklet to run.
|
|
*/
|
|
static void sa11x0_dma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&c->vc.lock, flags);
|
|
if (vchan_issue_pending(&c->vc)) {
|
|
if (!c->phy) {
|
|
spin_lock(&d->lock);
|
|
if (list_empty(&c->node)) {
|
|
list_add_tail(&c->node, &d->chan_pending);
|
|
tasklet_schedule(&d->task);
|
|
dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
|
|
}
|
|
spin_unlock(&d->lock);
|
|
}
|
|
} else
|
|
dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
|
|
spin_unlock_irqrestore(&c->vc.lock, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *sa11x0_dma_prep_slave_sg(
|
|
struct dma_chan *chan, struct scatterlist *sg, unsigned int sglen,
|
|
enum dma_transfer_direction dir, unsigned long flags, void *context)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
struct sa11x0_dma_desc *txd;
|
|
struct scatterlist *sgent;
|
|
unsigned i, j = sglen;
|
|
size_t size = 0;
|
|
|
|
/* SA11x0 channels can only operate in their native direction */
|
|
if (dir != (c->ddar & DDAR_RW ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV)) {
|
|
dev_err(chan->device->dev, "vchan %p: bad DMA direction: DDAR:%08x dir:%u\n",
|
|
&c->vc, c->ddar, dir);
|
|
return NULL;
|
|
}
|
|
|
|
/* Do not allow zero-sized txds */
|
|
if (sglen == 0)
|
|
return NULL;
|
|
|
|
for_each_sg(sg, sgent, sglen, i) {
|
|
dma_addr_t addr = sg_dma_address(sgent);
|
|
unsigned int len = sg_dma_len(sgent);
|
|
|
|
if (len > DMA_MAX_SIZE)
|
|
j += DIV_ROUND_UP(len, DMA_MAX_SIZE & ~DMA_ALIGN) - 1;
|
|
if (addr & DMA_ALIGN) {
|
|
dev_dbg(chan->device->dev, "vchan %p: bad buffer alignment: %pad\n",
|
|
&c->vc, &addr);
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
txd = kzalloc(sizeof(*txd) + j * sizeof(txd->sg[0]), GFP_ATOMIC);
|
|
if (!txd) {
|
|
dev_dbg(chan->device->dev, "vchan %p: kzalloc failed\n", &c->vc);
|
|
return NULL;
|
|
}
|
|
|
|
j = 0;
|
|
for_each_sg(sg, sgent, sglen, i) {
|
|
dma_addr_t addr = sg_dma_address(sgent);
|
|
unsigned len = sg_dma_len(sgent);
|
|
|
|
size += len;
|
|
|
|
do {
|
|
unsigned tlen = len;
|
|
|
|
/*
|
|
* Check whether the transfer will fit. If not, try
|
|
* to split the transfer up such that we end up with
|
|
* equal chunks - but make sure that we preserve the
|
|
* alignment. This avoids small segments.
|
|
*/
|
|
if (tlen > DMA_MAX_SIZE) {
|
|
unsigned mult = DIV_ROUND_UP(tlen,
|
|
DMA_MAX_SIZE & ~DMA_ALIGN);
|
|
|
|
tlen = (tlen / mult) & ~DMA_ALIGN;
|
|
}
|
|
|
|
txd->sg[j].addr = addr;
|
|
txd->sg[j].len = tlen;
|
|
|
|
addr += tlen;
|
|
len -= tlen;
|
|
j++;
|
|
} while (len);
|
|
}
|
|
|
|
txd->ddar = c->ddar;
|
|
txd->size = size;
|
|
txd->sglen = j;
|
|
|
|
dev_dbg(chan->device->dev, "vchan %p: txd %p: size %zu nr %u\n",
|
|
&c->vc, &txd->vd, txd->size, txd->sglen);
|
|
|
|
return vchan_tx_prep(&c->vc, &txd->vd, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *sa11x0_dma_prep_dma_cyclic(
|
|
struct dma_chan *chan, dma_addr_t addr, size_t size, size_t period,
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
struct sa11x0_dma_desc *txd;
|
|
unsigned i, j, k, sglen, sgperiod;
|
|
|
|
/* SA11x0 channels can only operate in their native direction */
|
|
if (dir != (c->ddar & DDAR_RW ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV)) {
|
|
dev_err(chan->device->dev, "vchan %p: bad DMA direction: DDAR:%08x dir:%u\n",
|
|
&c->vc, c->ddar, dir);
|
|
return NULL;
|
|
}
|
|
|
|
sgperiod = DIV_ROUND_UP(period, DMA_MAX_SIZE & ~DMA_ALIGN);
|
|
sglen = size * sgperiod / period;
|
|
|
|
/* Do not allow zero-sized txds */
|
|
if (sglen == 0)
|
|
return NULL;
|
|
|
|
txd = kzalloc(sizeof(*txd) + sglen * sizeof(txd->sg[0]), GFP_ATOMIC);
|
|
if (!txd) {
|
|
dev_dbg(chan->device->dev, "vchan %p: kzalloc failed\n", &c->vc);
|
|
return NULL;
|
|
}
|
|
|
|
for (i = k = 0; i < size / period; i++) {
|
|
size_t tlen, len = period;
|
|
|
|
for (j = 0; j < sgperiod; j++, k++) {
|
|
tlen = len;
|
|
|
|
if (tlen > DMA_MAX_SIZE) {
|
|
unsigned mult = DIV_ROUND_UP(tlen, DMA_MAX_SIZE & ~DMA_ALIGN);
|
|
tlen = (tlen / mult) & ~DMA_ALIGN;
|
|
}
|
|
|
|
txd->sg[k].addr = addr;
|
|
txd->sg[k].len = tlen;
|
|
addr += tlen;
|
|
len -= tlen;
|
|
}
|
|
|
|
WARN_ON(len != 0);
|
|
}
|
|
|
|
WARN_ON(k != sglen);
|
|
|
|
txd->ddar = c->ddar;
|
|
txd->size = size;
|
|
txd->sglen = sglen;
|
|
txd->cyclic = 1;
|
|
txd->period = sgperiod;
|
|
|
|
return vchan_tx_prep(&c->vc, &txd->vd, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
}
|
|
|
|
static int sa11x0_dma_device_config(struct dma_chan *chan,
|
|
struct dma_slave_config *cfg)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
u32 ddar = c->ddar & ((0xf << 4) | DDAR_RW);
|
|
dma_addr_t addr;
|
|
enum dma_slave_buswidth width;
|
|
u32 maxburst;
|
|
|
|
if (ddar & DDAR_RW) {
|
|
addr = cfg->src_addr;
|
|
width = cfg->src_addr_width;
|
|
maxburst = cfg->src_maxburst;
|
|
} else {
|
|
addr = cfg->dst_addr;
|
|
width = cfg->dst_addr_width;
|
|
maxburst = cfg->dst_maxburst;
|
|
}
|
|
|
|
if ((width != DMA_SLAVE_BUSWIDTH_1_BYTE &&
|
|
width != DMA_SLAVE_BUSWIDTH_2_BYTES) ||
|
|
(maxburst != 4 && maxburst != 8))
|
|
return -EINVAL;
|
|
|
|
if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
|
|
ddar |= DDAR_DW;
|
|
if (maxburst == 8)
|
|
ddar |= DDAR_BS;
|
|
|
|
dev_dbg(c->vc.chan.device->dev, "vchan %p: dma_slave_config addr %pad width %u burst %u\n",
|
|
&c->vc, &addr, width, maxburst);
|
|
|
|
c->ddar = ddar | (addr & 0xf0000000) | (addr & 0x003ffffc) << 6;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa11x0_dma_device_pause(struct dma_chan *chan)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
|
|
struct sa11x0_dma_phy *p;
|
|
LIST_HEAD(head);
|
|
unsigned long flags;
|
|
|
|
dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
|
|
spin_lock_irqsave(&c->vc.lock, flags);
|
|
if (c->status == DMA_IN_PROGRESS) {
|
|
c->status = DMA_PAUSED;
|
|
|
|
p = c->phy;
|
|
if (p) {
|
|
writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C);
|
|
} else {
|
|
spin_lock(&d->lock);
|
|
list_del_init(&c->node);
|
|
spin_unlock(&d->lock);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&c->vc.lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa11x0_dma_device_resume(struct dma_chan *chan)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
|
|
struct sa11x0_dma_phy *p;
|
|
LIST_HEAD(head);
|
|
unsigned long flags;
|
|
|
|
dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
|
|
spin_lock_irqsave(&c->vc.lock, flags);
|
|
if (c->status == DMA_PAUSED) {
|
|
c->status = DMA_IN_PROGRESS;
|
|
|
|
p = c->phy;
|
|
if (p) {
|
|
writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_S);
|
|
} else if (!list_empty(&c->vc.desc_issued)) {
|
|
spin_lock(&d->lock);
|
|
list_add_tail(&c->node, &d->chan_pending);
|
|
spin_unlock(&d->lock);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&c->vc.lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa11x0_dma_device_terminate_all(struct dma_chan *chan)
|
|
{
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
|
|
struct sa11x0_dma_phy *p;
|
|
LIST_HEAD(head);
|
|
unsigned long flags;
|
|
|
|
dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
|
|
/* Clear the tx descriptor lists */
|
|
spin_lock_irqsave(&c->vc.lock, flags);
|
|
vchan_get_all_descriptors(&c->vc, &head);
|
|
|
|
p = c->phy;
|
|
if (p) {
|
|
dev_dbg(d->slave.dev, "pchan %u: terminating\n", p->num);
|
|
/* vchan is assigned to a pchan - stop the channel */
|
|
writel(DCSR_RUN | DCSR_IE |
|
|
DCSR_STRTA | DCSR_DONEA |
|
|
DCSR_STRTB | DCSR_DONEB,
|
|
p->base + DMA_DCSR_C);
|
|
|
|
if (p->txd_load) {
|
|
if (p->txd_load != p->txd_done)
|
|
list_add_tail(&p->txd_load->vd.node, &head);
|
|
p->txd_load = NULL;
|
|
}
|
|
if (p->txd_done) {
|
|
list_add_tail(&p->txd_done->vd.node, &head);
|
|
p->txd_done = NULL;
|
|
}
|
|
c->phy = NULL;
|
|
spin_lock(&d->lock);
|
|
p->vchan = NULL;
|
|
spin_unlock(&d->lock);
|
|
tasklet_schedule(&d->task);
|
|
}
|
|
spin_unlock_irqrestore(&c->vc.lock, flags);
|
|
vchan_dma_desc_free_list(&c->vc, &head);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct sa11x0_dma_channel_desc {
|
|
u32 ddar;
|
|
const char *name;
|
|
};
|
|
|
|
#define CD(d1, d2) { .ddar = DDAR_##d1 | d2, .name = #d1 }
|
|
static const struct sa11x0_dma_channel_desc chan_desc[] = {
|
|
CD(Ser0UDCTr, 0),
|
|
CD(Ser0UDCRc, DDAR_RW),
|
|
CD(Ser1SDLCTr, 0),
|
|
CD(Ser1SDLCRc, DDAR_RW),
|
|
CD(Ser1UARTTr, 0),
|
|
CD(Ser1UARTRc, DDAR_RW),
|
|
CD(Ser2ICPTr, 0),
|
|
CD(Ser2ICPRc, DDAR_RW),
|
|
CD(Ser3UARTTr, 0),
|
|
CD(Ser3UARTRc, DDAR_RW),
|
|
CD(Ser4MCP0Tr, 0),
|
|
CD(Ser4MCP0Rc, DDAR_RW),
|
|
CD(Ser4MCP1Tr, 0),
|
|
CD(Ser4MCP1Rc, DDAR_RW),
|
|
CD(Ser4SSPTr, 0),
|
|
CD(Ser4SSPRc, DDAR_RW),
|
|
};
|
|
|
|
static int sa11x0_dma_init_dmadev(struct dma_device *dmadev,
|
|
struct device *dev)
|
|
{
|
|
unsigned i;
|
|
|
|
INIT_LIST_HEAD(&dmadev->channels);
|
|
dmadev->dev = dev;
|
|
dmadev->device_free_chan_resources = sa11x0_dma_free_chan_resources;
|
|
dmadev->device_config = sa11x0_dma_device_config;
|
|
dmadev->device_pause = sa11x0_dma_device_pause;
|
|
dmadev->device_resume = sa11x0_dma_device_resume;
|
|
dmadev->device_terminate_all = sa11x0_dma_device_terminate_all;
|
|
dmadev->device_tx_status = sa11x0_dma_tx_status;
|
|
dmadev->device_issue_pending = sa11x0_dma_issue_pending;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(chan_desc); i++) {
|
|
struct sa11x0_dma_chan *c;
|
|
|
|
c = kzalloc(sizeof(*c), GFP_KERNEL);
|
|
if (!c) {
|
|
dev_err(dev, "no memory for channel %u\n", i);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
c->status = DMA_IN_PROGRESS;
|
|
c->ddar = chan_desc[i].ddar;
|
|
c->name = chan_desc[i].name;
|
|
INIT_LIST_HEAD(&c->node);
|
|
|
|
c->vc.desc_free = sa11x0_dma_free_desc;
|
|
vchan_init(&c->vc, dmadev);
|
|
}
|
|
|
|
return dma_async_device_register(dmadev);
|
|
}
|
|
|
|
static int sa11x0_dma_request_irq(struct platform_device *pdev, int nr,
|
|
void *data)
|
|
{
|
|
int irq = platform_get_irq(pdev, nr);
|
|
|
|
if (irq <= 0)
|
|
return -ENXIO;
|
|
|
|
return request_irq(irq, sa11x0_dma_irq, 0, dev_name(&pdev->dev), data);
|
|
}
|
|
|
|
static void sa11x0_dma_free_irq(struct platform_device *pdev, int nr,
|
|
void *data)
|
|
{
|
|
int irq = platform_get_irq(pdev, nr);
|
|
if (irq > 0)
|
|
free_irq(irq, data);
|
|
}
|
|
|
|
static void sa11x0_dma_free_channels(struct dma_device *dmadev)
|
|
{
|
|
struct sa11x0_dma_chan *c, *cn;
|
|
|
|
list_for_each_entry_safe(c, cn, &dmadev->channels, vc.chan.device_node) {
|
|
list_del(&c->vc.chan.device_node);
|
|
tasklet_kill(&c->vc.task);
|
|
kfree(c);
|
|
}
|
|
}
|
|
|
|
static int sa11x0_dma_probe(struct platform_device *pdev)
|
|
{
|
|
struct sa11x0_dma_dev *d;
|
|
struct resource *res;
|
|
unsigned i;
|
|
int ret;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENXIO;
|
|
|
|
d = kzalloc(sizeof(*d), GFP_KERNEL);
|
|
if (!d) {
|
|
ret = -ENOMEM;
|
|
goto err_alloc;
|
|
}
|
|
|
|
spin_lock_init(&d->lock);
|
|
INIT_LIST_HEAD(&d->chan_pending);
|
|
|
|
d->base = ioremap(res->start, resource_size(res));
|
|
if (!d->base) {
|
|
ret = -ENOMEM;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
tasklet_init(&d->task, sa11x0_dma_tasklet, (unsigned long)d);
|
|
|
|
for (i = 0; i < NR_PHY_CHAN; i++) {
|
|
struct sa11x0_dma_phy *p = &d->phy[i];
|
|
|
|
p->dev = d;
|
|
p->num = i;
|
|
p->base = d->base + i * DMA_SIZE;
|
|
writel_relaxed(DCSR_RUN | DCSR_IE | DCSR_ERROR |
|
|
DCSR_DONEA | DCSR_STRTA | DCSR_DONEB | DCSR_STRTB,
|
|
p->base + DMA_DCSR_C);
|
|
writel_relaxed(0, p->base + DMA_DDAR);
|
|
|
|
ret = sa11x0_dma_request_irq(pdev, i, p);
|
|
if (ret) {
|
|
while (i) {
|
|
i--;
|
|
sa11x0_dma_free_irq(pdev, i, &d->phy[i]);
|
|
}
|
|
goto err_irq;
|
|
}
|
|
}
|
|
|
|
dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
|
|
d->slave.device_prep_slave_sg = sa11x0_dma_prep_slave_sg;
|
|
d->slave.device_prep_dma_cyclic = sa11x0_dma_prep_dma_cyclic;
|
|
d->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
d->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
|
d->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES);
|
|
d->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES);
|
|
ret = sa11x0_dma_init_dmadev(&d->slave, &pdev->dev);
|
|
if (ret) {
|
|
dev_warn(d->slave.dev, "failed to register slave async device: %d\n",
|
|
ret);
|
|
goto err_slave_reg;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, d);
|
|
return 0;
|
|
|
|
err_slave_reg:
|
|
sa11x0_dma_free_channels(&d->slave);
|
|
for (i = 0; i < NR_PHY_CHAN; i++)
|
|
sa11x0_dma_free_irq(pdev, i, &d->phy[i]);
|
|
err_irq:
|
|
tasklet_kill(&d->task);
|
|
iounmap(d->base);
|
|
err_ioremap:
|
|
kfree(d);
|
|
err_alloc:
|
|
return ret;
|
|
}
|
|
|
|
static int sa11x0_dma_remove(struct platform_device *pdev)
|
|
{
|
|
struct sa11x0_dma_dev *d = platform_get_drvdata(pdev);
|
|
unsigned pch;
|
|
|
|
dma_async_device_unregister(&d->slave);
|
|
|
|
sa11x0_dma_free_channels(&d->slave);
|
|
for (pch = 0; pch < NR_PHY_CHAN; pch++)
|
|
sa11x0_dma_free_irq(pdev, pch, &d->phy[pch]);
|
|
tasklet_kill(&d->task);
|
|
iounmap(d->base);
|
|
kfree(d);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa11x0_dma_suspend(struct device *dev)
|
|
{
|
|
struct sa11x0_dma_dev *d = dev_get_drvdata(dev);
|
|
unsigned pch;
|
|
|
|
for (pch = 0; pch < NR_PHY_CHAN; pch++) {
|
|
struct sa11x0_dma_phy *p = &d->phy[pch];
|
|
u32 dcsr, saved_dcsr;
|
|
|
|
dcsr = saved_dcsr = readl_relaxed(p->base + DMA_DCSR_R);
|
|
if (dcsr & DCSR_RUN) {
|
|
writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C);
|
|
dcsr = readl_relaxed(p->base + DMA_DCSR_R);
|
|
}
|
|
|
|
saved_dcsr &= DCSR_RUN | DCSR_IE;
|
|
if (dcsr & DCSR_BIU) {
|
|
p->dbs[0] = readl_relaxed(p->base + DMA_DBSB);
|
|
p->dbt[0] = readl_relaxed(p->base + DMA_DBTB);
|
|
p->dbs[1] = readl_relaxed(p->base + DMA_DBSA);
|
|
p->dbt[1] = readl_relaxed(p->base + DMA_DBTA);
|
|
saved_dcsr |= (dcsr & DCSR_STRTA ? DCSR_STRTB : 0) |
|
|
(dcsr & DCSR_STRTB ? DCSR_STRTA : 0);
|
|
} else {
|
|
p->dbs[0] = readl_relaxed(p->base + DMA_DBSA);
|
|
p->dbt[0] = readl_relaxed(p->base + DMA_DBTA);
|
|
p->dbs[1] = readl_relaxed(p->base + DMA_DBSB);
|
|
p->dbt[1] = readl_relaxed(p->base + DMA_DBTB);
|
|
saved_dcsr |= dcsr & (DCSR_STRTA | DCSR_STRTB);
|
|
}
|
|
p->dcsr = saved_dcsr;
|
|
|
|
writel(DCSR_STRTA | DCSR_STRTB, p->base + DMA_DCSR_C);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sa11x0_dma_resume(struct device *dev)
|
|
{
|
|
struct sa11x0_dma_dev *d = dev_get_drvdata(dev);
|
|
unsigned pch;
|
|
|
|
for (pch = 0; pch < NR_PHY_CHAN; pch++) {
|
|
struct sa11x0_dma_phy *p = &d->phy[pch];
|
|
struct sa11x0_dma_desc *txd = NULL;
|
|
u32 dcsr = readl_relaxed(p->base + DMA_DCSR_R);
|
|
|
|
WARN_ON(dcsr & (DCSR_BIU | DCSR_STRTA | DCSR_STRTB | DCSR_RUN));
|
|
|
|
if (p->txd_done)
|
|
txd = p->txd_done;
|
|
else if (p->txd_load)
|
|
txd = p->txd_load;
|
|
|
|
if (!txd)
|
|
continue;
|
|
|
|
writel_relaxed(txd->ddar, p->base + DMA_DDAR);
|
|
|
|
writel_relaxed(p->dbs[0], p->base + DMA_DBSA);
|
|
writel_relaxed(p->dbt[0], p->base + DMA_DBTA);
|
|
writel_relaxed(p->dbs[1], p->base + DMA_DBSB);
|
|
writel_relaxed(p->dbt[1], p->base + DMA_DBTB);
|
|
writel_relaxed(p->dcsr, p->base + DMA_DCSR_S);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops sa11x0_dma_pm_ops = {
|
|
.suspend_noirq = sa11x0_dma_suspend,
|
|
.resume_noirq = sa11x0_dma_resume,
|
|
.freeze_noirq = sa11x0_dma_suspend,
|
|
.thaw_noirq = sa11x0_dma_resume,
|
|
.poweroff_noirq = sa11x0_dma_suspend,
|
|
.restore_noirq = sa11x0_dma_resume,
|
|
};
|
|
|
|
static struct platform_driver sa11x0_dma_driver = {
|
|
.driver = {
|
|
.name = "sa11x0-dma",
|
|
.pm = &sa11x0_dma_pm_ops,
|
|
},
|
|
.probe = sa11x0_dma_probe,
|
|
.remove = sa11x0_dma_remove,
|
|
};
|
|
|
|
bool sa11x0_dma_filter_fn(struct dma_chan *chan, void *param)
|
|
{
|
|
if (chan->device->dev->driver == &sa11x0_dma_driver.driver) {
|
|
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
|
const char *p = param;
|
|
|
|
return !strcmp(c->name, p);
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(sa11x0_dma_filter_fn);
|
|
|
|
static int __init sa11x0_dma_init(void)
|
|
{
|
|
return platform_driver_register(&sa11x0_dma_driver);
|
|
}
|
|
subsys_initcall(sa11x0_dma_init);
|
|
|
|
static void __exit sa11x0_dma_exit(void)
|
|
{
|
|
platform_driver_unregister(&sa11x0_dma_driver);
|
|
}
|
|
module_exit(sa11x0_dma_exit);
|
|
|
|
MODULE_AUTHOR("Russell King");
|
|
MODULE_DESCRIPTION("SA-11x0 DMA driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:sa11x0-dma");
|