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![Minghuan Lian](/assets/img/avatar_default.png)
For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC SPI interrupts which can be associated with different Core. So we can support affinity to improve the performance. The MSI message data is a byte for Layerscape MSI. 7 6 5 4 3 2 1 0 | - | IBS | SRS | SRS bit0-1 is to select a MSIR which is associated with a CPU. IBS bit2-6 of ls1046, bit2-4 of ls1043a v1.1 is to select bit of the MSIR. With affinity, only bits of MSIR0(srs=0 cpu0) are available. All other bits of the MSIR1-3(cpu1-3) are reserved. The MSI hwirq always equals bit index of the MSIR0. When changing affinity, MSI message data will be appended corresponding SRS then MSI will be moved to the corresponding core. But in affinity mode, there is only 8 MSI interrupts for a controller of LS1043a v1.1. It cannot meet the requirement of the some PCIe devices such as 4 ports Ethernet card. In contrast, without affinity, all MSIRs can be used for core 0, the MSI interrupts can up to 32. So the parameter is added to control affinity mode. "lsmsi=no-affinity" will disable affinity and increase MSI interrupt number. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
428 lines
11 KiB
C
428 lines
11 KiB
C
/*
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* Freescale SCFG MSI(-X) support
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*
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* Copyright (C) 2016 Freescale Semiconductor.
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*
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* Author: Minghuan Lian <Minghuan.Lian@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/spinlock.h>
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#define MSI_IRQS_PER_MSIR 32
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#define MSI_MSIR_OFFSET 4
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#define MSI_LS1043V1_1_IRQS_PER_MSIR 8
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#define MSI_LS1043V1_1_MSIR_OFFSET 0x10
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struct ls_scfg_msi_cfg {
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u32 ibs_shift; /* Shift of interrupt bit select */
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u32 msir_irqs; /* The irq number per MSIR */
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u32 msir_base; /* The base address of MSIR */
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};
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struct ls_scfg_msir {
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struct ls_scfg_msi *msi_data;
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unsigned int index;
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unsigned int gic_irq;
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unsigned int bit_start;
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unsigned int bit_end;
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unsigned int srs; /* Shared interrupt register select */
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void __iomem *reg;
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};
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struct ls_scfg_msi {
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spinlock_t lock;
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struct platform_device *pdev;
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struct irq_domain *parent;
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struct irq_domain *msi_domain;
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void __iomem *regs;
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phys_addr_t msiir_addr;
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struct ls_scfg_msi_cfg *cfg;
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u32 msir_num;
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struct ls_scfg_msir *msir;
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u32 irqs_num;
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unsigned long *used;
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};
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static struct irq_chip ls_scfg_msi_irq_chip = {
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.name = "MSI",
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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static struct msi_domain_info ls_scfg_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
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MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX),
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.chip = &ls_scfg_msi_irq_chip,
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};
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static int msi_affinity_flag = 1;
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static int __init early_parse_ls_scfg_msi(char *p)
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{
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if (p && strncmp(p, "no-affinity", 11) == 0)
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msi_affinity_flag = 0;
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else
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msi_affinity_flag = 1;
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return 0;
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}
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early_param("lsmsi", early_parse_ls_scfg_msi);
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static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
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msg->address_hi = upper_32_bits(msi_data->msiir_addr);
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msg->address_lo = lower_32_bits(msi_data->msiir_addr);
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msg->data = data->hwirq;
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if (msi_affinity_flag)
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msg->data |= cpumask_first(data->common->affinity);
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}
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static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
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u32 cpu;
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if (!msi_affinity_flag)
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return -EINVAL;
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if (!force)
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cpu = cpumask_any_and(mask, cpu_online_mask);
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else
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cpu = cpumask_first(mask);
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if (cpu >= msi_data->msir_num)
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return -EINVAL;
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if (msi_data->msir[cpu].gic_irq <= 0) {
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pr_warn("cannot bind the irq to cpu%d\n", cpu);
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return -EINVAL;
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}
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cpumask_copy(irq_data->common->affinity, mask);
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return IRQ_SET_MASK_OK;
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}
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static struct irq_chip ls_scfg_msi_parent_chip = {
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.name = "SCFG",
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.irq_compose_msi_msg = ls_scfg_msi_compose_msg,
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.irq_set_affinity = ls_scfg_msi_set_affinity,
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};
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static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *args)
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{
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struct ls_scfg_msi *msi_data = domain->host_data;
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int pos, err = 0;
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WARN_ON(nr_irqs != 1);
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spin_lock(&msi_data->lock);
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pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
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if (pos < msi_data->irqs_num)
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__set_bit(pos, msi_data->used);
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else
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err = -ENOSPC;
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spin_unlock(&msi_data->lock);
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if (err)
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return err;
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irq_domain_set_info(domain, virq, pos,
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&ls_scfg_msi_parent_chip, msi_data,
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handle_simple_irq, NULL, NULL);
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return 0;
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}
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static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
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int pos;
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pos = d->hwirq;
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if (pos < 0 || pos >= msi_data->irqs_num) {
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pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
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return;
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}
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spin_lock(&msi_data->lock);
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__clear_bit(pos, msi_data->used);
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spin_unlock(&msi_data->lock);
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}
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static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
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.alloc = ls_scfg_msi_domain_irq_alloc,
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.free = ls_scfg_msi_domain_irq_free,
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};
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static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
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{
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struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
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struct ls_scfg_msi *msi_data = msir->msi_data;
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unsigned long val;
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int pos, size, virq, hwirq;
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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val = ioread32be(msir->reg);
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pos = msir->bit_start;
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size = msir->bit_end + 1;
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for_each_set_bit_from(pos, &val, size) {
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hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
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msir->srs;
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virq = irq_find_mapping(msi_data->parent, hwirq);
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if (virq)
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generic_handle_irq(virq);
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}
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chained_irq_exit(irq_desc_get_chip(desc), desc);
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}
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static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
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{
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/* Initialize MSI domain parent */
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msi_data->parent = irq_domain_add_linear(NULL,
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msi_data->irqs_num,
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&ls_scfg_msi_domain_ops,
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msi_data);
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if (!msi_data->parent) {
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dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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msi_data->msi_domain = pci_msi_create_irq_domain(
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of_node_to_fwnode(msi_data->pdev->dev.of_node),
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&ls_scfg_msi_domain_info,
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msi_data->parent);
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if (!msi_data->msi_domain) {
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dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n");
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irq_domain_remove(msi_data->parent);
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return -ENOMEM;
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}
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return 0;
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}
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static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
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{
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struct ls_scfg_msir *msir;
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int virq, i, hwirq;
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virq = platform_get_irq(msi_data->pdev, index);
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if (virq <= 0)
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return -ENODEV;
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msir = &msi_data->msir[index];
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msir->index = index;
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msir->msi_data = msi_data;
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msir->gic_irq = virq;
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msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
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if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
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msir->bit_start = 32 - ((msir->index + 1) *
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MSI_LS1043V1_1_IRQS_PER_MSIR);
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msir->bit_end = msir->bit_start +
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MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
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} else {
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msir->bit_start = 0;
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msir->bit_end = msi_data->cfg->msir_irqs - 1;
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}
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irq_set_chained_handler_and_data(msir->gic_irq,
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ls_scfg_msi_irq_handler,
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msir);
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if (msi_affinity_flag) {
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/* Associate MSIR interrupt to the cpu */
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irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
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msir->srs = 0; /* This value is determined by the CPU */
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} else
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msir->srs = index;
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/* Release the hwirqs corresponding to this MSIR */
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if (!msi_affinity_flag || msir->index == 0) {
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for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
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hwirq = i << msi_data->cfg->ibs_shift | msir->index;
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bitmap_clear(msi_data->used, hwirq, 1);
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}
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}
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return 0;
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}
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static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
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{
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struct ls_scfg_msi *msi_data = msir->msi_data;
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int i, hwirq;
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if (msir->gic_irq > 0)
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irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
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for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
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hwirq = i << msi_data->cfg->ibs_shift | msir->index;
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bitmap_set(msi_data->used, hwirq, 1);
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}
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return 0;
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}
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static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
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.ibs_shift = 3,
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.msir_irqs = MSI_IRQS_PER_MSIR,
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.msir_base = MSI_MSIR_OFFSET,
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};
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static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
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.ibs_shift = 2,
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.msir_irqs = MSI_IRQS_PER_MSIR,
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.msir_base = MSI_MSIR_OFFSET,
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};
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static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
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.ibs_shift = 2,
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.msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
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.msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
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};
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static const struct of_device_id ls_scfg_msi_id[] = {
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/* The following two misspelled compatibles are obsolete */
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{ .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
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{ .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
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{ .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
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{ .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
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{ .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
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{ .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
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{},
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};
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MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
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static int ls_scfg_msi_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct ls_scfg_msi *msi_data;
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struct resource *res;
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int i, ret;
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match = of_match_device(ls_scfg_msi_id, &pdev->dev);
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if (!match)
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return -ENODEV;
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msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
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if (!msi_data)
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return -ENOMEM;
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msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(msi_data->regs)) {
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dev_err(&pdev->dev, "failed to initialize 'regs'\n");
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return PTR_ERR(msi_data->regs);
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}
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msi_data->msiir_addr = res->start;
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msi_data->pdev = pdev;
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spin_lock_init(&msi_data->lock);
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msi_data->irqs_num = MSI_IRQS_PER_MSIR *
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(1 << msi_data->cfg->ibs_shift);
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msi_data->used = devm_kcalloc(&pdev->dev,
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BITS_TO_LONGS(msi_data->irqs_num),
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sizeof(*msi_data->used),
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GFP_KERNEL);
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if (!msi_data->used)
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return -ENOMEM;
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/*
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* Reserve all the hwirqs
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* The available hwirqs will be released in ls1_msi_setup_hwirq()
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*/
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bitmap_set(msi_data->used, 0, msi_data->irqs_num);
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msi_data->msir_num = of_irq_count(pdev->dev.of_node);
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if (msi_affinity_flag) {
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u32 cpu_num;
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cpu_num = num_possible_cpus();
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if (msi_data->msir_num >= cpu_num)
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msi_data->msir_num = cpu_num;
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else
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msi_affinity_flag = 0;
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}
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msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
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sizeof(*msi_data->msir),
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GFP_KERNEL);
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if (!msi_data->msir)
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return -ENOMEM;
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for (i = 0; i < msi_data->msir_num; i++)
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ls_scfg_msi_setup_hwirq(msi_data, i);
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ret = ls_scfg_msi_domains_init(msi_data);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, msi_data);
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return 0;
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}
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static int ls_scfg_msi_remove(struct platform_device *pdev)
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{
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struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
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int i;
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for (i = 0; i < msi_data->msir_num; i++)
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ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
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irq_domain_remove(msi_data->msi_domain);
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irq_domain_remove(msi_data->parent);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver ls_scfg_msi_driver = {
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.driver = {
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.name = "ls-scfg-msi",
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.of_match_table = ls_scfg_msi_id,
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},
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.probe = ls_scfg_msi_probe,
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.remove = ls_scfg_msi_remove,
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};
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module_platform_driver(ls_scfg_msi_driver);
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MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@nxp.com>");
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MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver");
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MODULE_LICENSE("GPL v2");
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