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Document the devicetree bindings for Socionext Milbeaut XDMAC controller. Controller only supports Mem->Mem transfers. Number of physical channels are determined by the number of irqs registered. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033157.14656-1-jassisinghbrar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
24 lines
727 B
Text
24 lines
727 B
Text
* Milbeaut AXI DMA Controller
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Milbeaut AXI DMA controller has only memory to memory transfer capability.
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* DMA controller
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Required property:
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- compatible: Should be "socionext,milbeaut-m10v-xdmac"
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain all of the per-channel DMA interrupts.
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Number of channels is configurable - 2, 4 or 8, so
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the number of interrupts specified should be {2,4,8}.
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- #dma-cells: Should be 1.
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Example:
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xdmac0: dma-controller@1c250000 {
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compatible = "socionext,milbeaut-m10v-xdmac";
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reg = <0x1c250000 0x1000>;
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interrupts = <0 17 0x4>,
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<0 18 0x4>,
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<0 19 0x4>,
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<0 20 0x4>;
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#dma-cells = <1>;
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};
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