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![Russell King](/assets/img/avatar_default.png)
BSYM() was invented to allow us to work around a problem with the assembler, where local symbols resolved by the assembler for the 'adr' instruction did not take account of their ISA. Since we don't want BSYM() used elsewhere, replace BSYM() with a new macro 'badr', which is like the 'adr' pseudo-op, but with the BSYM() mechanics integrated into it. This ensures that the BSYM()-ification is only used in conjunction with 'adr'. Acked-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
233 lines
5.3 KiB
ArmAsm
233 lines
5.3 KiB
ArmAsm
/*
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* arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
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*
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* Created by: Nicolas Pitre, March 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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* Refer to Documentation/arm/cluster-pm-race-avoidance.txt
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* for details of the synchronisation algorithms used here.
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*/
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#include <linux/linkage.h>
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#include <asm/mcpm.h>
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#include <asm/assembler.h>
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#include "vlock.h"
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.if MCPM_SYNC_CLUSTER_CPUS
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.error "cpus must be the first member of struct mcpm_sync_struct"
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.endif
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.macro pr_dbg string
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#if defined(CONFIG_DEBUG_LL) && defined(DEBUG)
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b 1901f
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1902: .asciz "CPU"
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1903: .asciz " cluster"
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1904: .asciz ": \string"
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.align
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1901: adr r0, 1902b
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bl printascii
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mov r0, r9
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bl printhex2
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adr r0, 1903b
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bl printascii
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mov r0, r10
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bl printhex2
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adr r0, 1904b
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bl printascii
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#endif
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.endm
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.arm
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.align
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ENTRY(mcpm_entry_point)
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ARM_BE8(setend be)
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THUMB( badr r12, 1f )
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THUMB( bx r12 )
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THUMB( .thumb )
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1:
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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ubfx r9, r0, #0, #8 @ r9 = cpu
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ubfx r10, r0, #8, #8 @ r10 = cluster
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mov r3, #MAX_CPUS_PER_CLUSTER
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mla r4, r3, r10, r9 @ r4 = canonical CPU index
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cmp r4, #(MAX_CPUS_PER_CLUSTER * MAX_NR_CLUSTERS)
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blo 2f
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/* We didn't expect this CPU. Try to cheaply make it quiet. */
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1: wfi
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wfe
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b 1b
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2: pr_dbg "kernel mcpm_entry_point\n"
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/*
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* MMU is off so we need to get to various variables in a
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* position independent way.
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*/
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adr r5, 3f
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ldmia r5, {r0, r6, r7, r8, r11}
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add r0, r5, r0 @ r0 = mcpm_entry_early_pokes
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add r6, r5, r6 @ r6 = mcpm_entry_vectors
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ldr r7, [r5, r7] @ r7 = mcpm_power_up_setup_phys
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add r8, r5, r8 @ r8 = mcpm_sync
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add r11, r5, r11 @ r11 = first_man_locks
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@ Perform an early poke, if any
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add r0, r0, r4, lsl #3
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ldmia r0, {r0, r1}
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teq r0, #0
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strne r1, [r0]
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mov r0, #MCPM_SYNC_CLUSTER_SIZE
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mla r8, r0, r10, r8 @ r8 = sync cluster base
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@ Signal that this CPU is coming UP:
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mov r0, #CPU_COMING_UP
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mov r5, #MCPM_SYNC_CPU_SIZE
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mla r5, r9, r5, r8 @ r5 = sync cpu address
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strb r0, [r5]
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@ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
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@ state, because there is at least one active CPU (this CPU).
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mov r0, #VLOCK_SIZE
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mla r11, r0, r10, r11 @ r11 = cluster first man lock
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mov r0, r11
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mov r1, r9 @ cpu
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bl vlock_trylock @ implies DMB
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cmp r0, #0 @ failed to get the lock?
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bne mcpm_setup_wait @ wait for cluster setup if so
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ldrb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
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cmp r0, #CLUSTER_UP @ cluster already up?
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bne mcpm_setup @ if not, set up the cluster
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@ Otherwise, release the first man lock and skip setup:
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mov r0, r11
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bl vlock_unlock
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b mcpm_setup_complete
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mcpm_setup:
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@ Control dependency implies strb not observable before previous ldrb.
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@ Signal that the cluster is being brought up:
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mov r0, #INBOUND_COMING_UP
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strb r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
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dmb
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@ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
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@ point onwards will observe INBOUND_COMING_UP and abort.
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@ Wait for any previously-pending cluster teardown operations to abort
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@ or complete:
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mcpm_teardown_wait:
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ldrb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
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cmp r0, #CLUSTER_GOING_DOWN
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bne first_man_setup
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wfe
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b mcpm_teardown_wait
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first_man_setup:
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dmb
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@ If the outbound gave up before teardown started, skip cluster setup:
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cmp r0, #CLUSTER_UP
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beq mcpm_setup_leave
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@ power_up_setup is now responsible for setting up the cluster:
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cmp r7, #0
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mov r0, #1 @ second (cluster) affinity level
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blxne r7 @ Call power_up_setup if defined
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dmb
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mov r0, #CLUSTER_UP
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strb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
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dmb
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mcpm_setup_leave:
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@ Leave the cluster setup critical section:
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mov r0, #INBOUND_NOT_COMING_UP
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strb r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
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dsb st
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sev
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mov r0, r11
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bl vlock_unlock @ implies DMB
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b mcpm_setup_complete
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@ In the contended case, non-first men wait here for cluster setup
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@ to complete:
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mcpm_setup_wait:
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ldrb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
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cmp r0, #CLUSTER_UP
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wfene
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bne mcpm_setup_wait
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dmb
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mcpm_setup_complete:
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@ If a platform-specific CPU setup hook is needed, it is
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@ called from here.
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cmp r7, #0
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mov r0, #0 @ first (CPU) affinity level
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blxne r7 @ Call power_up_setup if defined
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dmb
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@ Mark the CPU as up:
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mov r0, #CPU_UP
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strb r0, [r5]
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@ Observability order of CPU_UP and opening of the gate does not matter.
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mcpm_entry_gated:
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ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
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cmp r5, #0
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wfeeq
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beq mcpm_entry_gated
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dmb
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pr_dbg "released\n"
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bx r5
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.align 2
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3: .word mcpm_entry_early_pokes - .
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.word mcpm_entry_vectors - 3b
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.word mcpm_power_up_setup_phys - 3b
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.word mcpm_sync - 3b
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.word first_man_locks - 3b
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ENDPROC(mcpm_entry_point)
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.bss
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.align CACHE_WRITEBACK_ORDER
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.type first_man_locks, #object
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first_man_locks:
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.space VLOCK_SIZE * MAX_NR_CLUSTERS
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.align CACHE_WRITEBACK_ORDER
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.type mcpm_entry_vectors, #object
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ENTRY(mcpm_entry_vectors)
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.space 4 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER
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.type mcpm_entry_early_pokes, #object
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ENTRY(mcpm_entry_early_pokes)
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.space 8 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER
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.type mcpm_power_up_setup_phys, #object
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ENTRY(mcpm_power_up_setup_phys)
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.space 4 @ set by mcpm_sync_init()
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