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![Arnd Bergmann](/assets/img/avatar_default.png)
This tries to clear up the confusion between integers and iomem pointers in the marvell pxa platform. MMIO addresses are supposed to be __iomem* values, in order to let the Linux type checking work correctly. This patch moves the cast to __iomem as far back as possible, to the place where the MMIO virtual address windows are defined. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
285 lines
7.7 KiB
C
285 lines
7.7 KiB
C
/*
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* linux/arch/arm/plat-pxa/mfp.c
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*
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* Multi-Function Pin Support
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*
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* Copyright (C) 2007 Marvell Internation Ltd.
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*
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* 2007-08-21: eric miao <eric.miao@marvell.com>
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* initial version
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <plat/mfp.h>
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#define MFPR_SIZE (PAGE_SIZE)
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/* MFPR register bit definitions */
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#define MFPR_PULL_SEL (0x1 << 15)
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#define MFPR_PULLUP_EN (0x1 << 14)
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#define MFPR_PULLDOWN_EN (0x1 << 13)
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#define MFPR_SLEEP_SEL (0x1 << 9)
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#define MFPR_SLEEP_OE_N (0x1 << 7)
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#define MFPR_EDGE_CLEAR (0x1 << 6)
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#define MFPR_EDGE_FALL_EN (0x1 << 5)
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#define MFPR_EDGE_RISE_EN (0x1 << 4)
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#define MFPR_SLEEP_DATA(x) ((x) << 8)
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#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
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#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
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#define MFPR_EDGE_NONE (0)
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#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
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#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
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#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
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/*
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* Table that determines the low power modes outputs, with actual settings
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* used in parentheses for don't-care values. Except for the float output,
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* the configured driven and pulled levels match, so if there is a need for
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* non-LPM pulled output, the same configuration could probably be used.
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*
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* Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
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* (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
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*
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* Input 0 X(0) X(0) X(0) 0
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* Drive 0 0 0 0 X(1) 0
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* Drive 1 0 1 X(1) 0 0
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* Pull hi (1) 1 X(1) 1 0 0
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* Pull lo (0) 1 X(0) 0 1 0
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* Z (float) 1 X(0) 0 0 0
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*/
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#define MFPR_LPM_INPUT (0)
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#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
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#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
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#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
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#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
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#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
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#define MFPR_LPM_MASK (0xe080)
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/*
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* The pullup and pulldown state of the MFP pin at run mode is by default
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* determined by the selected alternate function. In case that some buggy
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* devices need to override this default behavior, the definitions below
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* indicates the setting of corresponding MFPR bits
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*
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* Definition pull_sel pullup_en pulldown_en
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* MFPR_PULL_NONE 0 0 0
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* MFPR_PULL_LOW 1 0 1
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* MFPR_PULL_HIGH 1 1 0
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* MFPR_PULL_BOTH 1 1 1
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* MFPR_PULL_FLOAT 1 0 0
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*/
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#define MFPR_PULL_NONE (0)
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#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
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#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
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#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
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#define MFPR_PULL_FLOAT (MFPR_PULL_SEL)
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/* mfp_spin_lock is used to ensure that MFP register configuration
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* (most likely a read-modify-write operation) is atomic, and that
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* mfp_table[] is consistent
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*/
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static DEFINE_SPINLOCK(mfp_spin_lock);
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static void __iomem *mfpr_mmio_base;
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struct mfp_pin {
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unsigned long config; /* -1 for not configured */
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unsigned long mfpr_off; /* MFPRxx Register offset */
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unsigned long mfpr_run; /* Run-Mode Register Value */
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unsigned long mfpr_lpm; /* Low Power Mode Register Value */
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};
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static struct mfp_pin mfp_table[MFP_PIN_MAX];
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/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
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static const unsigned long mfpr_lpm[] = {
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MFPR_LPM_INPUT,
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MFPR_LPM_DRIVE_LOW,
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MFPR_LPM_DRIVE_HIGH,
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MFPR_LPM_PULL_LOW,
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MFPR_LPM_PULL_HIGH,
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MFPR_LPM_FLOAT,
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MFPR_LPM_INPUT,
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};
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/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
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static const unsigned long mfpr_pull[] = {
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MFPR_PULL_NONE,
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MFPR_PULL_LOW,
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MFPR_PULL_HIGH,
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MFPR_PULL_BOTH,
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MFPR_PULL_FLOAT,
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};
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/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
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static const unsigned long mfpr_edge[] = {
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MFPR_EDGE_NONE,
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MFPR_EDGE_RISE,
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MFPR_EDGE_FALL,
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MFPR_EDGE_BOTH,
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};
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#define mfpr_readl(off) \
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__raw_readl(mfpr_mmio_base + (off))
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#define mfpr_writel(off, val) \
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__raw_writel(val, mfpr_mmio_base + (off))
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#define mfp_configured(p) ((p)->config != -1)
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/*
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* perform a read-back of any valid MFPR register to make sure the
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* previous writings are finished
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*/
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static unsigned long mfpr_off_readback;
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#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback)
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static inline void __mfp_config_run(struct mfp_pin *p)
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{
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if (mfp_configured(p))
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mfpr_writel(p->mfpr_off, p->mfpr_run);
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}
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static inline void __mfp_config_lpm(struct mfp_pin *p)
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{
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if (mfp_configured(p)) {
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unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
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if (mfpr_clr != p->mfpr_run)
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mfpr_writel(p->mfpr_off, mfpr_clr);
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if (p->mfpr_lpm != mfpr_clr)
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mfpr_writel(p->mfpr_off, p->mfpr_lpm);
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}
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}
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void mfp_config(unsigned long *mfp_cfgs, int num)
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{
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unsigned long flags;
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int i;
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spin_lock_irqsave(&mfp_spin_lock, flags);
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for (i = 0; i < num; i++, mfp_cfgs++) {
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unsigned long tmp, c = *mfp_cfgs;
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struct mfp_pin *p;
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int pin, af, drv, lpm, edge, pull;
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pin = MFP_PIN(c);
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BUG_ON(pin >= MFP_PIN_MAX);
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p = &mfp_table[pin];
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af = MFP_AF(c);
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drv = MFP_DS(c);
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lpm = MFP_LPM_STATE(c);
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edge = MFP_LPM_EDGE(c);
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pull = MFP_PULL(c);
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/* run-mode pull settings will conflict with MFPR bits of
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* low power mode state, calculate mfpr_run and mfpr_lpm
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* individually if pull != MFP_PULL_NONE
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*/
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tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
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if (likely(pull == MFP_PULL_NONE)) {
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p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
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p->mfpr_lpm = p->mfpr_run;
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} else {
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p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
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p->mfpr_run = tmp | mfpr_pull[pull];
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}
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p->config = c; __mfp_config_run(p);
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}
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mfpr_sync();
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spin_unlock_irqrestore(&mfp_spin_lock, flags);
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}
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unsigned long mfp_read(int mfp)
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{
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unsigned long val, flags;
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BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX);
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spin_lock_irqsave(&mfp_spin_lock, flags);
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val = mfpr_readl(mfp_table[mfp].mfpr_off);
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spin_unlock_irqrestore(&mfp_spin_lock, flags);
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return val;
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}
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void mfp_write(int mfp, unsigned long val)
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{
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unsigned long flags;
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BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX);
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spin_lock_irqsave(&mfp_spin_lock, flags);
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mfpr_writel(mfp_table[mfp].mfpr_off, val);
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mfpr_sync();
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spin_unlock_irqrestore(&mfp_spin_lock, flags);
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}
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void __init mfp_init_base(void __iomem *mfpr_base)
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{
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int i;
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/* initialize the table with default - unconfigured */
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for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
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mfp_table[i].config = -1;
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mfpr_mmio_base = mfpr_base;
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}
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void __init mfp_init_addr(struct mfp_addr_map *map)
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{
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struct mfp_addr_map *p;
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unsigned long offset, flags;
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int i;
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spin_lock_irqsave(&mfp_spin_lock, flags);
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/* mfp offset for readback */
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mfpr_off_readback = map[0].offset;
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for (p = map; p->start != MFP_PIN_INVALID; p++) {
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offset = p->offset;
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i = p->start;
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do {
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mfp_table[i].mfpr_off = offset;
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mfp_table[i].mfpr_run = 0;
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mfp_table[i].mfpr_lpm = 0;
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offset += 4; i++;
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} while ((i <= p->end) && (p->end != -1));
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}
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spin_unlock_irqrestore(&mfp_spin_lock, flags);
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}
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void mfp_config_lpm(void)
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{
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struct mfp_pin *p = &mfp_table[0];
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int pin;
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for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
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__mfp_config_lpm(p);
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}
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void mfp_config_run(void)
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{
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struct mfp_pin *p = &mfp_table[0];
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int pin;
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for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
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__mfp_config_run(p);
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}
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