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![Wang Nan](/assets/img/avatar_default.png)
This patch utilizes the previously introduced checker to check register usage for probed ARM instruction and saves it in a mask. A further patch will use such information to avoid simulation or emulation. Signed-off-by: Wang Nan <wangnan0@huawei.com> Reviewed-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org>
521 lines
13 KiB
C
521 lines
13 KiB
C
/*
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* arch/arm/probes/decode.c
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*
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* Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
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*
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* Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
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* Copyright (C) 2006, 2007 Motorola Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/system_info.h>
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#include <asm/ptrace.h>
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#include <linux/bug.h>
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#include "decode.h"
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#ifndef find_str_pc_offset
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/*
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* For STR and STM instructions, an ARM core may choose to use either
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* a +8 or a +12 displacement from the current instruction's address.
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* Whichever value is chosen for a given core, it must be the same for
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* both instructions and may not change. This function measures it.
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*/
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int str_pc_offset;
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void __init find_str_pc_offset(void)
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{
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int addr, scratch, ret;
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__asm__ (
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"sub %[ret], pc, #4 \n\t"
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"str pc, %[addr] \n\t"
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"ldr %[scr], %[addr] \n\t"
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"sub %[ret], %[scr], %[ret] \n\t"
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: [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
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str_pc_offset = ret;
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}
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#endif /* !find_str_pc_offset */
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#ifndef test_load_write_pc_interworking
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bool load_write_pc_interworks;
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void __init test_load_write_pc_interworking(void)
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{
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int arch = cpu_architecture();
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BUG_ON(arch == CPU_ARCH_UNKNOWN);
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load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T;
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}
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#endif /* !test_load_write_pc_interworking */
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#ifndef test_alu_write_pc_interworking
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bool alu_write_pc_interworks;
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void __init test_alu_write_pc_interworking(void)
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{
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int arch = cpu_architecture();
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BUG_ON(arch == CPU_ARCH_UNKNOWN);
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alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7;
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}
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#endif /* !test_alu_write_pc_interworking */
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void __init arm_probes_decode_init(void)
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{
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find_str_pc_offset();
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test_load_write_pc_interworking();
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test_alu_write_pc_interworking();
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}
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static unsigned long __kprobes __check_eq(unsigned long cpsr)
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{
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return cpsr & PSR_Z_BIT;
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}
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static unsigned long __kprobes __check_ne(unsigned long cpsr)
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{
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return (~cpsr) & PSR_Z_BIT;
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}
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static unsigned long __kprobes __check_cs(unsigned long cpsr)
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{
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return cpsr & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_cc(unsigned long cpsr)
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{
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return (~cpsr) & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_mi(unsigned long cpsr)
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{
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return cpsr & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_pl(unsigned long cpsr)
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{
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return (~cpsr) & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_vs(unsigned long cpsr)
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{
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return cpsr & PSR_V_BIT;
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}
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static unsigned long __kprobes __check_vc(unsigned long cpsr)
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{
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return (~cpsr) & PSR_V_BIT;
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}
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static unsigned long __kprobes __check_hi(unsigned long cpsr)
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{
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cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
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return cpsr & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_ls(unsigned long cpsr)
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{
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cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
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return (~cpsr) & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_ge(unsigned long cpsr)
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{
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cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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return (~cpsr) & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_lt(unsigned long cpsr)
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{
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cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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return cpsr & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_gt(unsigned long cpsr)
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{
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unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
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return (~temp) & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_le(unsigned long cpsr)
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{
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unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
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return temp & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_al(unsigned long cpsr)
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{
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return true;
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}
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probes_check_cc * const probes_condition_checks[16] = {
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&__check_eq, &__check_ne, &__check_cs, &__check_cc,
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&__check_mi, &__check_pl, &__check_vs, &__check_vc,
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&__check_hi, &__check_ls, &__check_ge, &__check_lt,
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&__check_gt, &__check_le, &__check_al, &__check_al
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};
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void __kprobes probes_simulate_nop(probes_opcode_t opcode,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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}
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void __kprobes probes_emulate_none(probes_opcode_t opcode,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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asi->insn_fn();
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}
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/*
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* Prepare an instruction slot to receive an instruction for emulating.
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* This is done by placing a subroutine return after the location where the
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* instruction will be placed. We also modify ARM instructions to be
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* unconditional as the condition code will already be checked before any
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* emulation handler is called.
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*/
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static probes_opcode_t __kprobes
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prepare_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
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bool thumb)
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{
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#ifdef CONFIG_THUMB2_KERNEL
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if (thumb) {
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u16 *thumb_insn = (u16 *)asi->insn;
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/* Thumb bx lr */
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thumb_insn[1] = __opcode_to_mem_thumb16(0x4770);
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thumb_insn[2] = __opcode_to_mem_thumb16(0x4770);
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return insn;
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}
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asi->insn[1] = __opcode_to_mem_arm(0xe12fff1e); /* ARM bx lr */
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#else
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asi->insn[1] = __opcode_to_mem_arm(0xe1a0f00e); /* mov pc, lr */
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#endif
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/* Make an ARM instruction unconditional */
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if (insn < 0xe0000000)
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insn = (insn | 0xe0000000) & ~0x10000000;
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return insn;
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}
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/*
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* Write a (probably modified) instruction into the slot previously prepared by
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* prepare_emulated_insn
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*/
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static void __kprobes
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set_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
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bool thumb)
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{
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#ifdef CONFIG_THUMB2_KERNEL
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if (thumb) {
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u16 *ip = (u16 *)asi->insn;
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if (is_wide_instruction(insn))
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*ip++ = __opcode_to_mem_thumb16(insn >> 16);
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*ip++ = __opcode_to_mem_thumb16(insn);
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return;
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}
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#endif
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asi->insn[0] = __opcode_to_mem_arm(insn);
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}
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/*
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* When we modify the register numbers encoded in an instruction to be emulated,
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* the new values come from this define. For ARM and 32-bit Thumb instructions
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* this gives...
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*
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* bit position 16 12 8 4 0
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* ---------------+---+---+---+---+---+
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* register r2 r0 r1 -- r3
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*/
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#define INSN_NEW_BITS 0x00020103
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/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
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#define INSN_SAMEAS16_BITS 0x22222222
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/*
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* Validate and modify each of the registers encoded in an instruction.
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*
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* Each nibble in regs contains a value from enum decode_reg_type. For each
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* non-zero value, the corresponding nibble in pinsn is validated and modified
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* according to the type.
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*/
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static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify)
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{
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probes_opcode_t insn = *pinsn;
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probes_opcode_t mask = 0xf; /* Start at least significant nibble */
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for (; regs != 0; regs >>= 4, mask <<= 4) {
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probes_opcode_t new_bits = INSN_NEW_BITS;
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switch (regs & 0xf) {
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case REG_TYPE_NONE:
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/* Nibble not a register, skip to next */
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continue;
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case REG_TYPE_ANY:
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/* Any register is allowed */
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break;
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case REG_TYPE_SAMEAS16:
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/* Replace register with same as at bit position 16 */
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new_bits = INSN_SAMEAS16_BITS;
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break;
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case REG_TYPE_SP:
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/* Only allow SP (R13) */
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if ((insn ^ 0xdddddddd) & mask)
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goto reject;
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break;
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case REG_TYPE_PC:
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/* Only allow PC (R15) */
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if ((insn ^ 0xffffffff) & mask)
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goto reject;
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break;
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case REG_TYPE_NOSP:
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/* Reject SP (R13) */
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if (((insn ^ 0xdddddddd) & mask) == 0)
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goto reject;
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break;
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case REG_TYPE_NOSPPC:
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case REG_TYPE_NOSPPCX:
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/* Reject SP and PC (R13 and R15) */
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if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
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goto reject;
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break;
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case REG_TYPE_NOPCWB:
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if (!is_writeback(insn))
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break; /* No writeback, so any register is OK */
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/* fall through... */
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case REG_TYPE_NOPC:
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case REG_TYPE_NOPCX:
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/* Reject PC (R15) */
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if (((insn ^ 0xffffffff) & mask) == 0)
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goto reject;
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break;
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}
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/* Replace value of nibble with new register number... */
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insn &= ~mask;
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insn |= new_bits & mask;
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}
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if (modify)
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*pinsn = insn;
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return true;
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reject:
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return false;
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}
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static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
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[DECODE_TYPE_TABLE] = sizeof(struct decode_table),
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[DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom),
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[DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate),
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[DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate),
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[DECODE_TYPE_OR] = sizeof(struct decode_or),
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[DECODE_TYPE_REJECT] = sizeof(struct decode_reject)
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};
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static int run_checkers(const struct decode_checker *checkers[],
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int action, probes_opcode_t insn,
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struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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const struct decode_checker **p;
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if (!checkers)
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return INSN_GOOD;
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p = checkers;
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while (*p != NULL) {
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int retval;
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probes_check_t *checker_func = (*p)[action].checker;
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retval = INSN_GOOD;
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if (checker_func)
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retval = checker_func(insn, asi, h);
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if (retval == INSN_REJECTED)
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return retval;
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p++;
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}
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return INSN_GOOD;
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}
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/*
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* probes_decode_insn operates on data tables in order to decode an ARM
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* architecture instruction onto which a kprobe has been placed.
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*
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* These instruction decoding tables are a concatenation of entries each
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* of which consist of one of the following structs:
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*
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* decode_table
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* decode_custom
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* decode_simulate
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* decode_emulate
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* decode_or
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* decode_reject
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*
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* Each of these starts with a struct decode_header which has the following
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* fields:
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*
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* type_regs
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* mask
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* value
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*
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* The least significant DECODE_TYPE_BITS of type_regs contains a value
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* from enum decode_type, this indicates which of the decode_* structs
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* the entry contains. The value DECODE_TYPE_END indicates the end of the
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* table.
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*
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* When the table is parsed, each entry is checked in turn to see if it
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* matches the instruction to be decoded using the test:
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*
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* (insn & mask) == value
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*
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* If no match is found before the end of the table is reached then decoding
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* fails with INSN_REJECTED.
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*
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* When a match is found, decode_regs() is called to validate and modify each
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* of the registers encoded in the instruction; the data it uses to do this
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* is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
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* to fail with INSN_REJECTED.
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*
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* Once the instruction has passed the above tests, further processing
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* depends on the type of the table entry's decode struct.
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*
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*/
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int __kprobes
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probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
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const union decode_item *table, bool thumb,
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bool emulate, const union decode_action *actions,
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const struct decode_checker *checkers[])
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{
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const struct decode_header *h = (struct decode_header *)table;
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const struct decode_header *next;
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bool matched = false;
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/*
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* @insn can be modified by decode_regs. Save its original
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* value for checkers.
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*/
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probes_opcode_t origin_insn = insn;
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/*
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* stack_space is initialized to 0 here. Checker functions
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* should update is value if they find this is a stack store
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* instruction: positive value means bytes of stack usage,
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* negitive value means unable to determine stack usage
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* statically. For instruction doesn't store to stack, checker
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* do nothing with it.
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*/
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asi->stack_space = 0;
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/*
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* Similarly to stack_space, register_usage_flags is filled by
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* checkers. Its default value is set to ~0, which is 'all
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* registers are used', to prevent any potential optimization.
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*/
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asi->register_usage_flags = ~0UL;
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if (emulate)
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insn = prepare_emulated_insn(insn, asi, thumb);
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for (;; h = next) {
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enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
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u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
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if (type == DECODE_TYPE_END)
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return INSN_REJECTED;
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next = (struct decode_header *)
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((uintptr_t)h + decode_struct_sizes[type]);
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if (!matched && (insn & h->mask.bits) != h->value.bits)
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continue;
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if (!decode_regs(&insn, regs, emulate))
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return INSN_REJECTED;
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switch (type) {
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case DECODE_TYPE_TABLE: {
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struct decode_table *d = (struct decode_table *)h;
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next = (struct decode_header *)d->table.table;
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break;
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}
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case DECODE_TYPE_CUSTOM: {
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int err;
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struct decode_custom *d = (struct decode_custom *)h;
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int action = d->decoder.action;
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err = run_checkers(checkers, action, origin_insn, asi, h);
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if (err == INSN_REJECTED)
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return INSN_REJECTED;
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return actions[action].decoder(insn, asi, h);
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}
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case DECODE_TYPE_SIMULATE: {
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int err;
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struct decode_simulate *d = (struct decode_simulate *)h;
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int action = d->handler.action;
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err = run_checkers(checkers, action, origin_insn, asi, h);
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if (err == INSN_REJECTED)
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return INSN_REJECTED;
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asi->insn_handler = actions[action].handler;
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return INSN_GOOD_NO_SLOT;
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}
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case DECODE_TYPE_EMULATE: {
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int err;
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struct decode_emulate *d = (struct decode_emulate *)h;
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int action = d->handler.action;
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err = run_checkers(checkers, action, origin_insn, asi, h);
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if (err == INSN_REJECTED)
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return INSN_REJECTED;
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if (!emulate)
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return actions[action].decoder(insn, asi, h);
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asi->insn_handler = actions[action].handler;
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set_emulated_insn(insn, asi, thumb);
|
|
return INSN_GOOD;
|
|
}
|
|
|
|
case DECODE_TYPE_OR:
|
|
matched = true;
|
|
break;
|
|
|
|
case DECODE_TYPE_REJECT:
|
|
default:
|
|
return INSN_REJECTED;
|
|
}
|
|
}
|
|
}
|