mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-31 00:17:44 +00:00
6656920b0b
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/*
|
|
* include/asm-xtensa/tlb.h
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2001 - 2005 Tensilica Inc.
|
|
*/
|
|
|
|
#ifndef _XTENSA_TLB_H
|
|
#define _XTENSA_TLB_H
|
|
|
|
#include <asm/cache.h>
|
|
#include <asm/page.h>
|
|
|
|
#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
|
|
|
|
/* Note, read http://lkml.org/lkml/2004/1/15/6 */
|
|
|
|
# define tlb_start_vma(tlb,vma) do { } while (0)
|
|
# define tlb_end_vma(tlb,vma) do { } while (0)
|
|
|
|
#else
|
|
|
|
# define tlb_start_vma(tlb, vma) \
|
|
do { \
|
|
if (!tlb->fullmm) \
|
|
flush_cache_range(vma, vma->vm_start, vma->vm_end); \
|
|
} while(0)
|
|
|
|
# define tlb_end_vma(tlb, vma) \
|
|
do { \
|
|
if (!tlb->fullmm) \
|
|
flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
|
|
} while(0)
|
|
|
|
#endif
|
|
|
|
#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
|
|
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
|
|
|
|
#include <asm-generic/tlb.h>
|
|
|
|
#define __pte_free_tlb(tlb,pte) pte_free(pte)
|
|
|
|
#endif /* _XTENSA_TLB_H */
|