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8bbec86ce6
assigned-clocks are a dependency of clocks, however the dtschema has
limitation and expects clocks to be present in the binding using
assigned-clocks, not in other referenced bindings. The clocks were
defined in common fsl,imx6q-pcie-common.yaml, which is referenced by
fsl,imx6q-pcie-ep.yaml. The fsl,imx6q-pcie-ep.yaml used assigned-clocks
thus leading to warnings:
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.example.dtb: pcie-ep@33800000:
Unevaluated properties are not allowed ('assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' were unexpected)
From schema: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
Fix this by moving clocks to each specific schema from the common one
and narrowing them to strictly match what is expected for given device.
Fixes: b10f82380e ("dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/20230508071837.68552-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
270 lines
6.5 KiB
YAML
270 lines
6.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX6 PCIe RC/EP controller
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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- Richard Zhu <hongxing.zhu@nxp.com>
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description:
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Generic Freescale i.MX PCIe Root Port and Endpoint controller
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properties.
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properties:
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clocks:
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minItems: 3
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maxItems: 4
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clock-names:
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minItems: 3
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maxItems: 4
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num-lanes:
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const: 1
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fsl,imx7d-pcie-phy:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to an fsl,imx7d-pcie-phy node. Additional
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required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
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and imx8mq-pcie-ep.
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power-domains:
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minItems: 1
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items:
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- description: The phandle pointing to the DISPLAY domain for
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imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
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imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
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- description: The phandle pointing to the PCIE_PHY power domains
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for imx6sx-pcie and imx6sx-pcie-ep.
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power-domain-names:
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minItems: 1
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items:
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- const: pcie
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- const: pcie_phy
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resets:
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minItems: 2
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maxItems: 3
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description: Phandles to PCIe-related reset lines exposed by SRC
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IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,
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imx8mq-pcie, and imx8mq-pcie-ep.
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reset-names:
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minItems: 2
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maxItems: 3
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fsl,tx-deemph-gen1:
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description: Gen1 De-emphasis value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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fsl,tx-deemph-gen2-3p5db:
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description: Gen2 (3.5db) De-emphasis value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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fsl,tx-deemph-gen2-6db:
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description: Gen2 (6db) De-emphasis value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 20
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fsl,tx-swing-full:
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description: Gen2 TX SWING FULL value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 127
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fsl,tx-swing-low:
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description: TX launch amplitude swing_low value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 127
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fsl,max-link-speed:
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description: Specify PCI Gen for link capability (optional required).
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Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
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requirements and thus for gen2 capability a gen2 compliant clock
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generator should be used and configured.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 3, 4]
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default: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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vpcie-supply:
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description: Should specify the regulator in charge of PCIe port power.
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The regulator will be enabled when initializing the PCIe host and
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disabled either as part of the init process or when shutting down
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the host (optional required).
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vph-supply:
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description: Should specify the regulator in charge of VPH one of
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the three PCIe PHY powers. This regulator can be supplied by both
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1.8v and 3.3v voltage supplies (optional required).
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required:
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- clocks
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- clock-names
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- num-lanes
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx6sx-pcie-ep
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then:
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properties:
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clock-names:
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items:
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- {}
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- {}
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- const: pcie_phy
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- const: pcie_inbound_axi
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power-domains:
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minItems: 2
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power-domain-names:
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minItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8mq-pcie
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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clock-names:
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items:
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- {}
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- {}
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- const: pcie_phy
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- const: pcie_aux
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- if:
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properties:
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compatible:
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not:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx8mq-pcie
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- fsl,imx6sx-pcie-ep
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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- fsl,imx6q-pcie-ep
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- fsl,imx6qp-pcie-ep
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- fsl,imx7d-pcie-ep
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then:
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properties:
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clock-names:
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maxItems: 3
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contains:
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const: pcie_phy
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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- fsl,imx8mm-pcie-ep
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- fsl,imx8mp-pcie-ep
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then:
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properties:
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clock-names:
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maxItems: 3
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contains:
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const: pcie_aux
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx6q-pcie-ep
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- fsl,imx6qp-pcie-ep
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then:
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properties:
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power-domains: false
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power-domain-names: false
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx6sx-pcie-ep
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- fsl,imx6q-pcie-ep
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- fsl,imx6qp-pcie-ep
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then:
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properties:
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power-domains:
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maxItems: 1
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power-domain-names: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6sx-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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- fsl,imx8mq-pcie
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- fsl,imx6q-pcie-ep
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- fsl,imx6sx-pcie-ep
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- fsl,imx6qp-pcie-ep
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- fsl,imx7d-pcie-ep
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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resets:
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minItems: 3
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reset-names:
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items:
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- const: pciephy
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- const: apps
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- const: turnoff
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else:
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properties:
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: apps
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- const: turnoff
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additionalProperties: true
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...
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