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On some boards the 100MHz PCIe reference clock to both controller and devices is controllable. Add that clock to the list of clocks. The clock is optional, so the minItems stays the same. Link: https://lore.kernel.org/linux-pci/20231206145041.667900-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
217 lines
5.9 KiB
YAML
217 lines
5.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe controller on Rockchip SoCs
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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- Simon Xue <xxm@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |+
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RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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oneOf:
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- const: rockchip,rk3568-pcie
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- items:
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- enum:
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- rockchip,rk3588-pcie
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- const: rockchip,rk3568-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers
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- description: Rockchip designed configuration registers
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- description: Config registers
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reg-names:
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items:
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- const: dbi
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- const: apb
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- const: config
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clocks:
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minItems: 5
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items:
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- description: AHB clock for PCIe master
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- description: AHB clock for PCIe slave
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- description: AHB clock for PCIe dbi
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- description: APB clock for PCIe
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- description: Auxiliary clock for PCIe
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- description: PIPE clock
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- description: Reference clock for PCIe
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clock-names:
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minItems: 5
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items:
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- const: aclk_mst
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- const: aclk_slv
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- const: aclk_dbi
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- const: pclk
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- const: aux
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- const: pipe
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- const: ref
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interrupts:
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items:
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- description:
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Combined system interrupt, which is used to signal the following
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interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
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hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
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edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
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- description:
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Combined PM interrupt, which is used to signal the following
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interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
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linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
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linkst_out_l0s, pm_dstate_update
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- description:
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Combined message interrupt, which is used to signal the following
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interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
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pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
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- description:
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Combined legacy interrupt, which is used to signal the following
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interrupts - inta, intb, intc, intd
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- description:
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Combined error interrupt, which is used to signal the following
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interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
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tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
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nf_err_rx, f_err_rx, radm_qoverflow
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interrupt-names:
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items:
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- const: sys
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- const: pmc
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- const: msg
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- const: legacy
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- const: err
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legacy-interrupt-controller:
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description: Interrupt controller node for handling legacy PCI interrupts.
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type: object
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additionalProperties: false
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properties:
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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interrupt-controller: true
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interrupts:
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items:
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- description: combined legacy interrupt
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required:
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- "#address-cells"
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- "#interrupt-cells"
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- interrupt-controller
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- interrupts
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msi-map: true
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num-lanes: true
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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power-domains:
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maxItems: 1
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ranges:
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minItems: 2
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maxItems: 3
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- const: pipe
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- items:
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- const: pwr
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- const: pipe
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vpcie3v3-supply: true
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- msi-map
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- num-lanes
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- phys
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- phy-names
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- power-domains
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie3x2: pcie@fe280000 {
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0800000 0x0 0x390000>,
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<0x0 0xfe280000 0x0 0x10000>,
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<0x3 0x80000000 0x0 0x100000>;
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reg-names = "dbi", "apb", "config";
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bus-range = <0x20 0x2f>;
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clocks = <&cru 143>, <&cru 144>,
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<&cru 145>, <&cru 146>,
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<&cru 147>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux";
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device_type = "pci";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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linux,pci-domain = <2>;
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max-link-speed = <2>;
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msi-map = <0x2000 &its 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power 15>;
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ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
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<0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
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resets = <&cru 193>;
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reset-names = "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
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};
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};
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};
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...
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