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6d06779e86
Having allowed the user to define a set of engines that they will want to only use, we go one step further and allow them to bind those engines into a single virtual instance. Submitting a batch to the virtual engine will then forward it to any one of the set in a manner as best to distribute load. The virtual engine has a single timeline across all engines (it operates as a single queue), so it is not able to concurrently run batches across multiple engines by itself; that is left up to the user to submit multiple concurrent batches to multiple queues. Multiple users will be load balanced across the system. The mechanism used for load balancing in this patch is a late greedy balancer. When a request is ready for execution, it is added to each engine's queue, and when an engine is ready for its next request it claims it from the virtual engine. The first engine to do so, wins, i.e. the request is executed at the earliest opportunity (idle moment) in the system. As not all HW is created equal, the user is still able to skip the virtual engine and execute the batch on a specific engine, all within the same queue. It will then be executed in order on the correct engine, with execution on other virtual engines being moved away due to the load detection. A couple of areas for potential improvement left! - The virtual engine always take priority over equal-priority tasks. Mostly broken up by applying FQ_CODEL rules for prioritising new clients, and hopefully the virtual and real engines are not then congested (i.e. all work is via virtual engines, or all work is to the real engine). - We require the breadcrumb irq around every virtual engine request. For normal engines, we eliminate the need for the slow round trip via interrupt by using the submit fence and queueing in order. For virtual engines, we have to allow any job to transfer to a new ring, and cannot coalesce the submissions, so require the completion fence instead, forcing the persistent use of interrupts. - We only drip feed single requests through each virtual engine and onto the physical engines, even if there was enough work to fill all ELSP, leaving small stalls with an idle CS event at the end of every request. Could we be greedy and fill both slots? Being lazy is virtuous for load distribution on less-than-full workloads though. Other areas of improvement are more general, such as reducing lock contention, reducing dispatch overhead, looking at direct submission rather than bouncing around tasklets etc. sseu: Lift the restriction to allow sseu to be reconfigured on virtual engines composed of RENDER_CLASS (rcs). v2: macroize check_user_mbz() v3: Cancel virtual engines on wedging v4: Commence commenting v5: Replace 64b sibling_mask with a list of class:instance v6: Drop the one-element array in the uabi v7: Assert it is an virtual engine in to_virtual_engine() v8: Skip over holes in [class][inst] so we can selftest with (vcs0, vcs2) Link: https://github.com/intel/media-driver/pull/283 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190521211134.16117-6-chris@chris-wilson.co.uk
99 lines
3 KiB
C
99 lines
3 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef __I915_GEM_H__
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#define __I915_GEM_H__
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#include <linux/bug.h>
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#include <linux/interrupt.h>
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struct drm_i915_private;
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#ifdef CONFIG_DRM_I915_DEBUG_GEM
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#define GEM_SHOW_DEBUG() (drm_debug & DRM_UT_DRIVER)
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#define GEM_BUG_ON(condition) do { if (unlikely((condition))) { \
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pr_err("%s:%d GEM_BUG_ON(%s)\n", \
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__func__, __LINE__, __stringify(condition)); \
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GEM_TRACE("%s:%d GEM_BUG_ON(%s)\n", \
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__func__, __LINE__, __stringify(condition)); \
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BUG(); \
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} \
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} while(0)
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#define GEM_WARN_ON(expr) WARN_ON(expr)
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#define GEM_DEBUG_DECL(var) var
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#define GEM_DEBUG_EXEC(expr) expr
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#define GEM_DEBUG_BUG_ON(expr) GEM_BUG_ON(expr)
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#define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
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#else
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#define GEM_SHOW_DEBUG() (0)
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#define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
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#define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
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#define GEM_DEBUG_DECL(var)
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#define GEM_DEBUG_EXEC(expr) do { } while (0)
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#define GEM_DEBUG_BUG_ON(expr)
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#define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
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#endif
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#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
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#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
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#define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
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#define GEM_TRACE_DUMP_ON(expr) \
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do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
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#else
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#define GEM_TRACE(...) do { } while (0)
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#define GEM_TRACE_DUMP() do { } while (0)
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#define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr)
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#endif
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#define I915_GEM_IDLE_TIMEOUT (HZ / 5)
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static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
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{
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if (!atomic_fetch_inc(&t->count))
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tasklet_unlock_wait(t);
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}
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static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
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{
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return !atomic_read(&t->count);
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}
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static inline bool __tasklet_enable(struct tasklet_struct *t)
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{
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return atomic_dec_and_test(&t->count);
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}
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static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
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{
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return test_bit(TASKLET_STATE_SCHED, &t->state);
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}
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#endif /* __I915_GEM_H__ */
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