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![Chris Wilson](/assets/img/avatar_default.png)
In the current scheme, on submitting a request we take a single global GEM wakeref, which trickles down to wake up all GT power domains. This is undesirable as we would like to be able to localise our power management to the available power domains and to remove the global GEM operations from the heart of the driver. (The intent there is to push global GEM decisions to the boundary as used by the GEM user interface.) Now during request construction, each request is responsible via its logical context to acquire a wakeref on each power domain it intends to utilize. Currently, each request takes a wakeref on the engine(s) and the engines themselves take a chipset wakeref. This gives us a transition on each engine which we can extend if we want to insert more powermangement control (such as soft rc6). The global GEM operations that currently require a struct_mutex are reduced to listening to pm events from the chipset GT wakeref. As we reduce the struct_mutex requirement, these listeners should evaporate. Perhaps the biggest immediate change is that this removes the struct_mutex requirement around GT power management, allowing us greater flexibility in request construction. Another important knock-on effect, is that by tracking engine usage, we can insert a switch back to the kernel context on that engine immediately, avoiding any extra delay or inserting global synchronisation barriers. This makes tracking when an engine and its associated contexts are idle much easier -- important for when we forgo our assumed execution ordering and need idle barriers to unpin used contexts. In the process, it means we remove a large chunk of code whose only purpose was to switch back to the kernel context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
312 lines
7.1 KiB
C
312 lines
7.1 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright <20> 2008-2018 Intel Corporation
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*/
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#ifndef _I915_GPU_ERROR_H_
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#define _I915_GPU_ERROR_H_
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#include <linux/kref.h>
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#include <linux/ktime.h>
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#include <linux/sched.h>
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#include <drm/drm_mm.h>
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#include "gt/intel_engine.h"
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#include "intel_device_info.h"
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#include "intel_uc_fw.h"
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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
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#include "i915_params.h"
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#include "i915_scheduler.h"
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struct drm_i915_private;
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struct intel_overlay_error_state;
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struct intel_display_error_state;
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struct i915_gpu_state {
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struct kref ref;
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ktime_t time;
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ktime_t boottime;
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ktime_t uptime;
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unsigned long capture;
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unsigned long epoch;
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struct drm_i915_private *i915;
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char error_msg[128];
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bool simulated;
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bool awake;
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bool wakelock;
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bool suspended;
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int iommu;
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u32 reset_count;
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u32 suspend_count;
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struct intel_device_info device_info;
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struct intel_runtime_info runtime_info;
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struct intel_driver_caps driver_caps;
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struct i915_params params;
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struct i915_error_uc {
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struct intel_uc_fw guc_fw;
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struct intel_uc_fw huc_fw;
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struct drm_i915_error_object *guc_log;
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} uc;
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/* Generic register state */
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u32 eir;
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u32 pgtbl_er;
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u32 ier;
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u32 gtier[6], ngtier;
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u32 ccid;
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u32 derrmr;
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u32 forcewake;
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u32 error; /* gen6+ */
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u32 err_int; /* gen7 */
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u32 fault_data0; /* gen8, gen9 */
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u32 fault_data1; /* gen8, gen9 */
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u32 done_reg;
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u32 gac_eco;
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u32 gam_ecochk;
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u32 gab_ctl;
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u32 gfx_mode;
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u32 nfence;
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u64 fence[I915_MAX_NUM_FENCES];
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struct intel_overlay_error_state *overlay;
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struct intel_display_error_state *display;
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struct drm_i915_error_engine {
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int engine_id;
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/* Software tracked state */
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bool idle;
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unsigned long hangcheck_timestamp;
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struct i915_address_space *vm;
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int num_requests;
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u32 reset_count;
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/* position of active request inside the ring */
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u32 rq_head, rq_post, rq_tail;
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/* our own tracking of ring head and tail */
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u32 cpu_ring_head;
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u32 cpu_ring_tail;
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/* Register state */
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u32 start;
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u32 tail;
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u32 head;
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u32 ctl;
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u32 mode;
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u32 hws;
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u32 ipeir;
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u32 ipehr;
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u32 bbstate;
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u32 instpm;
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u32 instps;
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u64 bbaddr;
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u64 acthd;
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u32 fault_reg;
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u64 faddr;
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u32 rc_psmi; /* sleep state */
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struct intel_instdone instdone;
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struct drm_i915_error_context {
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char comm[TASK_COMM_LEN];
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pid_t pid;
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u32 hw_id;
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int active;
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int guilty;
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struct i915_sched_attr sched_attr;
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} context;
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struct drm_i915_error_object {
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u64 gtt_offset;
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u64 gtt_size;
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int num_pages;
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int page_count;
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int unused;
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u32 *pages[0];
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} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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struct drm_i915_error_object **user_bo;
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long user_bo_count;
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struct drm_i915_error_object *wa_ctx;
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struct drm_i915_error_object *default_state;
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struct drm_i915_error_request {
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unsigned long flags;
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long jiffies;
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pid_t pid;
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u32 context;
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u32 seqno;
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u32 start;
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u32 head;
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u32 tail;
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struct i915_sched_attr sched_attr;
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} *requests, execlist[EXECLIST_MAX_PORTS];
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unsigned int num_ports;
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struct {
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u32 gfx_mode;
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union {
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u64 pdp[4];
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u32 pp_dir_base;
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};
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} vm_info;
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} engine[I915_NUM_ENGINES];
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struct drm_i915_error_buffer {
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u32 size;
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u32 name;
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u64 gtt_offset;
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u32 read_domains;
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u32 write_domain;
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s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
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u32 tiling:2;
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u32 dirty:1;
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u32 purgeable:1;
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u32 userptr:1;
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u32 cache_level:3;
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} *active_bo[I915_NUM_ENGINES], *pinned_bo;
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u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
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struct i915_address_space *active_vm[I915_NUM_ENGINES];
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struct scatterlist *sgl, *fit;
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};
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struct i915_gpu_error {
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/* For hangcheck timer */
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#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
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#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
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struct delayed_work hangcheck_work;
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/* For reset and error_state handling. */
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spinlock_t lock;
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/* Protected by the above dev->gpu_error.lock. */
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struct i915_gpu_state *first_error;
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atomic_t pending_fb_pin;
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/**
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* flags: Control various stages of the GPU reset
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*
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* #I915_RESET_BACKOFF - When we start a global reset, we need to
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* serialise with any other users attempting to do the same, and
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* any global resources that may be clobber by the reset (such as
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* FENCE registers).
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*
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* #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
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* acquire the struct_mutex to reset an engine, we need an explicit
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* flag to prevent two concurrent reset attempts in the same engine.
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* As the number of engines continues to grow, allocate the flags from
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* the most significant bits.
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*
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* #I915_WEDGED - If reset fails and we can no longer use the GPU,
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* we set the #I915_WEDGED bit. Prior to command submission, e.g.
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* i915_request_alloc(), this bit is checked and the sequence
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* aborted (with -EIO reported to userspace) if set.
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*/
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unsigned long flags;
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#define I915_RESET_BACKOFF 0
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#define I915_RESET_MODESET 1
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#define I915_RESET_ENGINE 2
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#define I915_WEDGED (BITS_PER_LONG - 1)
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/** Number of times the device has been reset (global) */
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u32 reset_count;
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/** Number of times an engine has been reset */
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u32 reset_engine_count[I915_NUM_ENGINES];
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struct mutex wedge_mutex; /* serialises wedging/unwedging */
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/**
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* Waitqueue to signal when a hang is detected. Used to for waiters
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* to release the struct_mutex for the reset to procede.
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*/
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wait_queue_head_t wait_queue;
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/**
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* Waitqueue to signal when the reset has completed. Used by clients
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* that wait for dev_priv->mm.wedged to settle.
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*/
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wait_queue_head_t reset_queue;
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struct srcu_struct reset_backoff_srcu;
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};
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struct drm_i915_error_state_buf {
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struct drm_i915_private *i915;
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struct scatterlist *sgl, *cur, *end;
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char *buf;
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size_t bytes;
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size_t size;
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loff_t iter;
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int err;
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};
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#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
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__printf(2, 3)
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void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
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struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
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void i915_capture_error_state(struct drm_i915_private *dev_priv,
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intel_engine_mask_t engine_mask,
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const char *error_msg);
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static inline struct i915_gpu_state *
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i915_gpu_state_get(struct i915_gpu_state *gpu)
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{
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kref_get(&gpu->ref);
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return gpu;
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}
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ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
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char *buf, loff_t offset, size_t count);
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void __i915_gpu_state_free(struct kref *kref);
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static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
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{
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if (gpu)
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kref_put(&gpu->ref, __i915_gpu_state_free);
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}
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struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
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void i915_reset_error_state(struct drm_i915_private *i915);
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void i915_disable_error_state(struct drm_i915_private *i915, int err);
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#else
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static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
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u32 engine_mask,
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const char *error_msg)
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{
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}
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static inline struct i915_gpu_state *
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i915_first_error_state(struct drm_i915_private *i915)
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{
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return ERR_PTR(-ENODEV);
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}
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static inline void i915_reset_error_state(struct drm_i915_private *i915)
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{
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}
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static inline void i915_disable_error_state(struct drm_i915_private *i915,
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int err)
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{
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}
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#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
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#endif /* _I915_GPU_ERROR_H_ */
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