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54c52a8412
Starting Gen11 GuC shares interrupt registers with SG unit instead of PM. But for now we don't care about SG interrupts. v2: (Chris) v3: rebased (Michal) v4: more bspec pages, use macros, update commit msg (Michal Wi) Bspec: 19820, 19840, 19841, 20176 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-13-michal.wajdeczko@intel.com
117 lines
4 KiB
C
117 lines
4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __I915_IRQ_H__
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#define __I915_IRQ_H__
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#include <linux/types.h>
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#include "i915_drv.h"
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struct drm_i915_private;
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struct intel_crtc;
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extern void intel_irq_init(struct drm_i915_private *dev_priv);
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extern void intel_irq_fini(struct drm_i915_private *dev_priv);
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int intel_irq_install(struct drm_i915_private *dev_priv);
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void intel_irq_uninstall(struct drm_i915_private *dev_priv);
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u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
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enum pipe pipe);
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void
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i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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u32 status_mask);
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void
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i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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u32 status_mask);
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
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void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
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void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
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u32 mask,
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u32 bits);
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void ilk_update_display_irq(struct drm_i915_private *dev_priv,
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void
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ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
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{
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ilk_update_display_irq(dev_priv, bits, bits);
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}
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static inline void
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ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
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{
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ilk_update_display_irq(dev_priv, bits, 0);
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}
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void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe, u32 bits)
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{
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bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
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}
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static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe, u32 bits)
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{
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bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
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}
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void
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ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
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{
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ibx_display_interrupt_update(dev_priv, bits, bits);
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}
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static inline void
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ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
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{
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ibx_display_interrupt_update(dev_priv, bits, 0);
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}
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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
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void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
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void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
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void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
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static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
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u32 mask)
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{
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return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
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}
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void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
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void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
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static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
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{
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/*
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* We only use drm_irq_uninstall() at unload and VT switch, so
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* this is the only thing we need to check.
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*/
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return dev_priv->runtime_pm.irqs_enabled;
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}
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int intel_get_crtc_scanline(struct intel_crtc *crtc);
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void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
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u8 pipe_mask);
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void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
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u8 pipe_mask);
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void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
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void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
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void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
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void gen11_reset_guc_interrupts(struct drm_i915_private *i915);
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void gen11_enable_guc_interrupts(struct drm_i915_private *i915);
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void gen11_disable_guc_interrupts(struct drm_i915_private *i915);
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#endif /* __I915_IRQ_H__ */
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