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![Lucas De Marchi](/assets/img/avatar_default.png)
In intel_package_header version 2 there's a new field in the fw_info table that must be 0, otherwise it's not the correct DMC firmware. Add a check for version 2 or later. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190607091230.1489-10-lucas.demarchi@intel.com
782 lines
20 KiB
C
782 lines
20 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_csr.h"
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/**
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* DOC: csr support for dmc
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*
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* Display Context Save and Restore (CSR) firmware support added from gen9
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* onwards to drive newly added DMC (Display microcontroller) in display
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* engine to save and restore the state of display engine when it enter into
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* low-power state and comes back to normal.
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*/
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#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
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#define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin"
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#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
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#define ICL_CSR_MAX_FW_SIZE 0x6000
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MODULE_FIRMWARE(ICL_CSR_PATH);
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#define CNL_CSR_PATH "i915/cnl_dmc_ver1_07.bin"
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#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
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#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
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MODULE_FIRMWARE(CNL_CSR_PATH);
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#define GLK_CSR_PATH "i915/glk_dmc_ver1_04.bin"
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#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
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#define GLK_CSR_MAX_FW_SIZE 0x4000
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MODULE_FIRMWARE(GLK_CSR_PATH);
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#define KBL_CSR_PATH "i915/kbl_dmc_ver1_04.bin"
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#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
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#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
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MODULE_FIRMWARE(KBL_CSR_PATH);
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#define SKL_CSR_PATH "i915/skl_dmc_ver1_27.bin"
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#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
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#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
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MODULE_FIRMWARE(SKL_CSR_PATH);
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#define BXT_CSR_PATH "i915/bxt_dmc_ver1_07.bin"
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#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
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#define BXT_CSR_MAX_FW_SIZE 0x3000
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MODULE_FIRMWARE(BXT_CSR_PATH);
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#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
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#define PACKAGE_MAX_FW_INFO_ENTRIES 20
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#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
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#define DMC_V1_MAX_MMIO_COUNT 8
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#define DMC_V3_MAX_MMIO_COUNT 20
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struct intel_css_header {
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/* 0x09 for DMC */
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u32 module_type;
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/* Includes the DMC specific header in dwords */
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u32 header_len;
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/* always value would be 0x10000 */
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u32 header_ver;
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/* Not used */
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u32 module_id;
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/* Not used */
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u32 module_vendor;
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/* in YYYYMMDD format */
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u32 date;
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/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
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u32 size;
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/* Not used */
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u32 key_size;
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/* Not used */
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u32 modulus_size;
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/* Not used */
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u32 exponent_size;
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/* Not used */
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u32 reserved1[12];
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/* Major Minor */
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u32 version;
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/* Not used */
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u32 reserved2[8];
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/* Not used */
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u32 kernel_header_info;
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} __packed;
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struct intel_fw_info {
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u8 reserved1;
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/* reserved on package_header version 1, must be 0 on version 2 */
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u8 dmc_id;
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/* Stepping (A, B, C, ..., *). * is a wildcard */
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char stepping;
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/* Sub-stepping (0, 1, ..., *). * is a wildcard */
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char substepping;
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u32 offset;
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u32 reserved2;
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} __packed;
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struct intel_package_header {
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/* DMC container header length in dwords */
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u8 header_len;
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/* 0x01, 0x02 */
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u8 header_ver;
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u8 reserved[10];
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/* Number of valid entries in the FWInfo array below */
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u32 num_entries;
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} __packed;
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struct intel_dmc_header_base {
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/* always value would be 0x40403E3E */
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u32 signature;
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/* DMC binary header length */
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u8 header_len;
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/* 0x01 */
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u8 header_ver;
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/* Reserved */
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u16 dmcc_ver;
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/* Major, Minor */
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u32 project;
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/* Firmware program size (excluding header) in dwords */
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u32 fw_size;
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/* Major Minor version */
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u32 fw_version;
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} __packed;
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struct intel_dmc_header_v1 {
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struct intel_dmc_header_base base;
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/* Number of valid MMIO cycles present. */
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u32 mmio_count;
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/* MMIO address */
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u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
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/* MMIO data */
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u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
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/* FW filename */
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char dfile[32];
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u32 reserved1[2];
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} __packed;
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struct intel_dmc_header_v3 {
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struct intel_dmc_header_base base;
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/* DMC RAM start MMIO address */
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u32 start_mmioaddr;
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u32 reserved[9];
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/* FW filename */
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char dfile[32];
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/* Number of valid MMIO cycles present. */
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u32 mmio_count;
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/* MMIO address */
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u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
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/* MMIO data */
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u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
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} __packed;
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struct stepping_info {
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char stepping;
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char substepping;
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};
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static const struct stepping_info skl_stepping_info[] = {
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{'A', '0'}, {'B', '0'}, {'C', '0'},
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{'D', '0'}, {'E', '0'}, {'F', '0'},
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{'G', '0'}, {'H', '0'}, {'I', '0'},
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{'J', '0'}, {'K', '0'}
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};
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static const struct stepping_info bxt_stepping_info[] = {
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{'A', '0'}, {'A', '1'}, {'A', '2'},
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{'B', '0'}, {'B', '1'}, {'B', '2'}
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};
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static const struct stepping_info icl_stepping_info[] = {
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{'A', '0'}, {'A', '1'}, {'A', '2'},
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{'B', '0'}, {'B', '2'},
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{'C', '0'}
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};
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static const struct stepping_info no_stepping_info = { '*', '*' };
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static const struct stepping_info *
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intel_get_stepping_info(struct drm_i915_private *dev_priv)
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{
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const struct stepping_info *si;
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unsigned int size;
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if (IS_ICELAKE(dev_priv)) {
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size = ARRAY_SIZE(icl_stepping_info);
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si = icl_stepping_info;
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} else if (IS_SKYLAKE(dev_priv)) {
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size = ARRAY_SIZE(skl_stepping_info);
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si = skl_stepping_info;
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} else if (IS_BROXTON(dev_priv)) {
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size = ARRAY_SIZE(bxt_stepping_info);
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si = bxt_stepping_info;
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} else {
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size = 0;
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si = NULL;
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}
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if (INTEL_REVID(dev_priv) < size)
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return si + INTEL_REVID(dev_priv);
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return &no_stepping_info;
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}
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static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
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{
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u32 val, mask;
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mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
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if (IS_GEN9_LP(dev_priv))
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mask |= DC_STATE_DEBUG_MASK_CORES;
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/* The below bit doesn't need to be cleared ever afterwards */
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val = I915_READ(DC_STATE_DEBUG);
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if ((val & mask) != mask) {
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val |= mask;
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I915_WRITE(DC_STATE_DEBUG, val);
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POSTING_READ(DC_STATE_DEBUG);
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}
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}
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/**
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* intel_csr_load_program() - write the firmware from memory to register.
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* @dev_priv: i915 drm device.
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*
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* CSR firmware is read from a .bin file and kept in internal memory one time.
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* Everytime display comes back from low power state this function is called to
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* copy the firmware from internal memory to registers.
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*/
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void intel_csr_load_program(struct drm_i915_private *dev_priv)
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{
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u32 *payload = dev_priv->csr.dmc_payload;
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u32 i, fw_size;
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if (!HAS_CSR(dev_priv)) {
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DRM_ERROR("No CSR support available for this platform\n");
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return;
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}
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if (!dev_priv->csr.dmc_payload) {
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DRM_ERROR("Tried to program CSR with empty payload\n");
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return;
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}
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fw_size = dev_priv->csr.dmc_fw_size;
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assert_rpm_wakelock_held(&dev_priv->runtime_pm);
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preempt_disable();
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for (i = 0; i < fw_size; i++)
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I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
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preempt_enable();
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for (i = 0; i < dev_priv->csr.mmio_count; i++) {
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I915_WRITE(dev_priv->csr.mmioaddr[i],
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dev_priv->csr.mmiodata[i]);
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}
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dev_priv->csr.dc_state = 0;
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gen9_set_dc_state_debugmask(dev_priv);
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}
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/*
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* Search fw_info table for dmc_offset to find firmware binary: num_entries is
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* already sanitized.
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*/
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static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
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unsigned int num_entries,
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const struct stepping_info *si,
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u8 package_ver)
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{
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u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
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unsigned int i;
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for (i = 0; i < num_entries; i++) {
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if (package_ver > 1 && fw_info[i].dmc_id != 0)
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continue;
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if (fw_info[i].substepping == '*' &&
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si->stepping == fw_info[i].stepping) {
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dmc_offset = fw_info[i].offset;
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break;
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}
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if (si->stepping == fw_info[i].stepping &&
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si->substepping == fw_info[i].substepping) {
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dmc_offset = fw_info[i].offset;
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break;
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}
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if (fw_info[i].stepping == '*' &&
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fw_info[i].substepping == '*') {
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/*
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* In theory we should stop the search as generic
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* entries should always come after the more specific
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* ones, but let's continue to make sure to work even
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* with "broken" firmwares. If we don't find a more
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* specific one, then we use this entry
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*/
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dmc_offset = fw_info[i].offset;
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}
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}
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return dmc_offset;
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}
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static u32 parse_csr_fw_dmc(struct intel_csr *csr,
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const struct intel_dmc_header_base *dmc_header,
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size_t rem_size)
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{
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unsigned int header_len_bytes, dmc_header_size, payload_size, i;
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const u32 *mmioaddr, *mmiodata;
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u32 mmio_count, mmio_count_max;
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u8 *payload;
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BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
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ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
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/*
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* Check if we can access common fields, we will checkc again below
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* after we have read the version
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*/
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if (rem_size < sizeof(struct intel_dmc_header_base))
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goto error_truncated;
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/* Cope with small differences between v1 and v3 */
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if (dmc_header->header_ver == 3) {
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const struct intel_dmc_header_v3 *v3 =
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(const struct intel_dmc_header_v3 *)dmc_header;
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if (rem_size < sizeof(struct intel_dmc_header_v3))
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goto error_truncated;
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mmioaddr = v3->mmioaddr;
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mmiodata = v3->mmiodata;
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mmio_count = v3->mmio_count;
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mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
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/* header_len is in dwords */
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header_len_bytes = dmc_header->header_len * 4;
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dmc_header_size = sizeof(*v3);
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} else if (dmc_header->header_ver == 1) {
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const struct intel_dmc_header_v1 *v1 =
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(const struct intel_dmc_header_v1 *)dmc_header;
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if (rem_size < sizeof(struct intel_dmc_header_v1))
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goto error_truncated;
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mmioaddr = v1->mmioaddr;
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mmiodata = v1->mmiodata;
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mmio_count = v1->mmio_count;
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mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
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header_len_bytes = dmc_header->header_len;
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dmc_header_size = sizeof(*v1);
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} else {
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DRM_ERROR("Unknown DMC fw header version: %u\n",
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dmc_header->header_ver);
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return 0;
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}
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if (header_len_bytes != dmc_header_size) {
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DRM_ERROR("DMC firmware has wrong dmc header length "
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"(%u bytes)\n", header_len_bytes);
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return 0;
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}
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/* Cache the dmc header info. */
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if (mmio_count > mmio_count_max) {
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DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
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return 0;
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}
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for (i = 0; i < mmio_count; i++) {
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if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
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mmioaddr[i] > CSR_MMIO_END_RANGE) {
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DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
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mmioaddr[i]);
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return 0;
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}
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csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
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csr->mmiodata[i] = mmiodata[i];
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}
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csr->mmio_count = mmio_count;
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rem_size -= header_len_bytes;
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/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
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payload_size = dmc_header->fw_size * 4;
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if (rem_size < payload_size)
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goto error_truncated;
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if (payload_size > csr->max_fw_size) {
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DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
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return 0;
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}
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csr->dmc_fw_size = dmc_header->fw_size;
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csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
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if (!csr->dmc_payload) {
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DRM_ERROR("Memory allocation failed for dmc payload\n");
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return 0;
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}
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payload = (u8 *)(dmc_header) + header_len_bytes;
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memcpy(csr->dmc_payload, payload, payload_size);
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return header_len_bytes + payload_size;
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error_truncated:
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DRM_ERROR("Truncated DMC firmware, refusing.\n");
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return 0;
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}
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static u32
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parse_csr_fw_package(struct intel_csr *csr,
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const struct intel_package_header *package_header,
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const struct stepping_info *si,
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size_t rem_size)
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{
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u32 package_size = sizeof(struct intel_package_header);
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u32 num_entries, max_entries, dmc_offset;
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const struct intel_fw_info *fw_info;
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if (rem_size < package_size)
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goto error_truncated;
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if (package_header->header_ver == 1) {
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max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
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} else if (package_header->header_ver == 2) {
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max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
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} else {
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DRM_ERROR("DMC firmware has unknown header version %u\n",
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package_header->header_ver);
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return 0;
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}
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/*
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|
* We should always have space for max_entries,
|
|
* even if not all are used
|
|
*/
|
|
package_size += max_entries * sizeof(struct intel_fw_info);
|
|
if (rem_size < package_size)
|
|
goto error_truncated;
|
|
|
|
if (package_header->header_len * 4 != package_size) {
|
|
DRM_ERROR("DMC firmware has wrong package header length "
|
|
"(%u bytes)\n", package_size);
|
|
return 0;
|
|
}
|
|
|
|
num_entries = package_header->num_entries;
|
|
if (WARN_ON(package_header->num_entries > max_entries))
|
|
num_entries = max_entries;
|
|
|
|
fw_info = (const struct intel_fw_info *)
|
|
((u8 *)package_header + sizeof(*package_header));
|
|
dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
|
|
package_header->header_ver);
|
|
if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
|
|
DRM_ERROR("DMC firmware not supported for %c stepping\n",
|
|
si->stepping);
|
|
return 0;
|
|
}
|
|
|
|
/* dmc_offset is in dwords */
|
|
return package_size + dmc_offset * 4;
|
|
|
|
error_truncated:
|
|
DRM_ERROR("Truncated DMC firmware, refusing.\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Return number of bytes parsed or 0 on error */
|
|
static u32 parse_csr_fw_css(struct intel_csr *csr,
|
|
struct intel_css_header *css_header,
|
|
size_t rem_size)
|
|
{
|
|
if (rem_size < sizeof(struct intel_css_header)) {
|
|
DRM_ERROR("Truncated DMC firmware, refusing.\n");
|
|
return 0;
|
|
}
|
|
|
|
if (sizeof(struct intel_css_header) !=
|
|
(css_header->header_len * 4)) {
|
|
DRM_ERROR("DMC firmware has wrong CSS header length "
|
|
"(%u bytes)\n",
|
|
(css_header->header_len * 4));
|
|
return 0;
|
|
}
|
|
|
|
if (csr->required_version &&
|
|
css_header->version != csr->required_version) {
|
|
DRM_INFO("Refusing to load DMC firmware v%u.%u,"
|
|
" please use v%u.%u\n",
|
|
CSR_VERSION_MAJOR(css_header->version),
|
|
CSR_VERSION_MINOR(css_header->version),
|
|
CSR_VERSION_MAJOR(csr->required_version),
|
|
CSR_VERSION_MINOR(csr->required_version));
|
|
return 0;
|
|
}
|
|
|
|
csr->version = css_header->version;
|
|
|
|
return sizeof(struct intel_css_header);
|
|
}
|
|
|
|
static void parse_csr_fw(struct drm_i915_private *dev_priv,
|
|
const struct firmware *fw)
|
|
{
|
|
struct intel_css_header *css_header;
|
|
struct intel_package_header *package_header;
|
|
struct intel_dmc_header_base *dmc_header;
|
|
struct intel_csr *csr = &dev_priv->csr;
|
|
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
|
|
u32 readcount = 0;
|
|
u32 r;
|
|
|
|
if (!fw)
|
|
return;
|
|
|
|
/* Extract CSS Header information */
|
|
css_header = (struct intel_css_header *)fw->data;
|
|
r = parse_csr_fw_css(csr, css_header, fw->size);
|
|
if (!r)
|
|
return;
|
|
|
|
readcount += r;
|
|
|
|
/* Extract Package Header information */
|
|
package_header = (struct intel_package_header *)&fw->data[readcount];
|
|
r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
|
|
if (!r)
|
|
return;
|
|
|
|
readcount += r;
|
|
|
|
/* Extract dmc_header information */
|
|
dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
|
|
parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
|
|
}
|
|
|
|
static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
|
|
{
|
|
WARN_ON(dev_priv->csr.wakeref);
|
|
dev_priv->csr.wakeref =
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
|
|
}
|
|
|
|
static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
|
|
{
|
|
intel_wakeref_t wakeref __maybe_unused =
|
|
fetch_and_zero(&dev_priv->csr.wakeref);
|
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
|
|
}
|
|
|
|
static void csr_load_work_fn(struct work_struct *work)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
struct intel_csr *csr;
|
|
const struct firmware *fw = NULL;
|
|
|
|
dev_priv = container_of(work, typeof(*dev_priv), csr.work);
|
|
csr = &dev_priv->csr;
|
|
|
|
request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
|
|
parse_csr_fw(dev_priv, fw);
|
|
|
|
if (dev_priv->csr.dmc_payload) {
|
|
intel_csr_load_program(dev_priv);
|
|
intel_csr_runtime_pm_put(dev_priv);
|
|
|
|
DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
|
|
dev_priv->csr.fw_path,
|
|
CSR_VERSION_MAJOR(csr->version),
|
|
CSR_VERSION_MINOR(csr->version));
|
|
} else {
|
|
dev_notice(dev_priv->drm.dev,
|
|
"Failed to load DMC firmware %s."
|
|
" Disabling runtime power management.\n",
|
|
csr->fw_path);
|
|
dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
|
|
INTEL_UC_FIRMWARE_URL);
|
|
}
|
|
|
|
release_firmware(fw);
|
|
}
|
|
|
|
/**
|
|
* intel_csr_ucode_init() - initialize the firmware loading.
|
|
* @dev_priv: i915 drm device.
|
|
*
|
|
* This function is called at the time of loading the display driver to read
|
|
* firmware from a .bin file and copied into a internal memory.
|
|
*/
|
|
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_csr *csr = &dev_priv->csr;
|
|
|
|
INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
|
|
|
|
if (!HAS_CSR(dev_priv))
|
|
return;
|
|
|
|
/*
|
|
* Obtain a runtime pm reference, until CSR is loaded, to avoid entering
|
|
* runtime-suspend.
|
|
*
|
|
* On error, we return with the rpm wakeref held to prevent runtime
|
|
* suspend as runtime suspend *requires* a working CSR for whatever
|
|
* reason.
|
|
*/
|
|
intel_csr_runtime_pm_get(dev_priv);
|
|
|
|
if (INTEL_GEN(dev_priv) >= 12) {
|
|
/* Allow to load fw via parameter using the last known size */
|
|
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
|
|
} else if (IS_GEN(dev_priv, 11)) {
|
|
csr->fw_path = ICL_CSR_PATH;
|
|
csr->required_version = ICL_CSR_VERSION_REQUIRED;
|
|
csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
|
|
} else if (IS_CANNONLAKE(dev_priv)) {
|
|
csr->fw_path = CNL_CSR_PATH;
|
|
csr->required_version = CNL_CSR_VERSION_REQUIRED;
|
|
csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
|
|
} else if (IS_GEMINILAKE(dev_priv)) {
|
|
csr->fw_path = GLK_CSR_PATH;
|
|
csr->required_version = GLK_CSR_VERSION_REQUIRED;
|
|
csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
|
|
} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
|
|
csr->fw_path = KBL_CSR_PATH;
|
|
csr->required_version = KBL_CSR_VERSION_REQUIRED;
|
|
csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
|
|
} else if (IS_SKYLAKE(dev_priv)) {
|
|
csr->fw_path = SKL_CSR_PATH;
|
|
csr->required_version = SKL_CSR_VERSION_REQUIRED;
|
|
csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
|
|
} else if (IS_BROXTON(dev_priv)) {
|
|
csr->fw_path = BXT_CSR_PATH;
|
|
csr->required_version = BXT_CSR_VERSION_REQUIRED;
|
|
csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
|
|
}
|
|
|
|
if (i915_modparams.dmc_firmware_path) {
|
|
if (strlen(i915_modparams.dmc_firmware_path) == 0) {
|
|
csr->fw_path = NULL;
|
|
DRM_INFO("Disabling CSR firmware and runtime PM\n");
|
|
return;
|
|
}
|
|
|
|
csr->fw_path = i915_modparams.dmc_firmware_path;
|
|
/* Bypass version check for firmware override. */
|
|
csr->required_version = 0;
|
|
}
|
|
|
|
if (csr->fw_path == NULL) {
|
|
DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
|
|
schedule_work(&dev_priv->csr.work);
|
|
}
|
|
|
|
/**
|
|
* intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
|
|
* @dev_priv: i915 drm device
|
|
*
|
|
* Prepare the DMC firmware before entering system suspend. This includes
|
|
* flushing pending work items and releasing any resources acquired during
|
|
* init.
|
|
*/
|
|
void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (!HAS_CSR(dev_priv))
|
|
return;
|
|
|
|
flush_work(&dev_priv->csr.work);
|
|
|
|
/* Drop the reference held in case DMC isn't loaded. */
|
|
if (!dev_priv->csr.dmc_payload)
|
|
intel_csr_runtime_pm_put(dev_priv);
|
|
}
|
|
|
|
/**
|
|
* intel_csr_ucode_resume() - init CSR firmware during system resume
|
|
* @dev_priv: i915 drm device
|
|
*
|
|
* Reinitialize the DMC firmware during system resume, reacquiring any
|
|
* resources released in intel_csr_ucode_suspend().
|
|
*/
|
|
void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (!HAS_CSR(dev_priv))
|
|
return;
|
|
|
|
/*
|
|
* Reacquire the reference to keep RPM disabled in case DMC isn't
|
|
* loaded.
|
|
*/
|
|
if (!dev_priv->csr.dmc_payload)
|
|
intel_csr_runtime_pm_get(dev_priv);
|
|
}
|
|
|
|
/**
|
|
* intel_csr_ucode_fini() - unload the CSR firmware.
|
|
* @dev_priv: i915 drm device.
|
|
*
|
|
* Firmmware unloading includes freeing the internal memory and reset the
|
|
* firmware loading status.
|
|
*/
|
|
void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (!HAS_CSR(dev_priv))
|
|
return;
|
|
|
|
intel_csr_ucode_suspend(dev_priv);
|
|
WARN_ON(dev_priv->csr.wakeref);
|
|
|
|
kfree(dev_priv->csr.dmc_payload);
|
|
}
|