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5d9814df0a
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the support for the dw_apb_timer into the arm64 defconfig. However, for some platforms like the Intel Stratix10 and Agilex, the clock manager doesn't get loaded until after the timer driver get loaded. Thus, the driver hits the panic "No clock nor clock-frequency property for" because it cannot properly get the clock. This patch adds the error handling needed for the timer driver so that the kernel can continue booting instead of just hitting the panic. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20201205105223.208604-1-dinguyen@kernel.org
193 lines
4.3 KiB
C
193 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Altera Corporation
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* Copyright (c) 2011 Picochip Ltd., Jamie Iles
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*
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* Modified from mach-picoxcell/time.c
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*/
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#include <linux/delay.h>
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#include <linux/dw_apb_timer.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/sched_clock.h>
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static int __init timer_get_base_and_rate(struct device_node *np,
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void __iomem **base, u32 *rate)
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{
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struct clk *timer_clk;
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struct clk *pclk;
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struct reset_control *rstc;
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int ret;
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*base = of_iomap(np, 0);
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if (!*base)
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panic("Unable to map regs for %pOFn", np);
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/*
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* Reset the timer if the reset control is available, wiping
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* out the state the firmware may have left it
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*/
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rstc = of_reset_control_get(np, NULL);
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if (!IS_ERR(rstc)) {
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reset_control_assert(rstc);
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reset_control_deassert(rstc);
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}
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/*
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* Not all implementations use a periphal clock, so don't panic
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* if it's not present
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*/
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pclk = of_clk_get_by_name(np, "pclk");
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if (!IS_ERR(pclk))
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if (clk_prepare_enable(pclk))
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pr_warn("pclk for %pOFn is present, but could not be activated\n",
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np);
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if (!of_property_read_u32(np, "clock-freq", rate) &&
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!of_property_read_u32(np, "clock-frequency", rate))
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return 0;
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timer_clk = of_clk_get_by_name(np, "timer");
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if (IS_ERR(timer_clk))
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return PTR_ERR(timer_clk);
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ret = clk_prepare_enable(timer_clk);
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if (ret)
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return ret;
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*rate = clk_get_rate(timer_clk);
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if (!(*rate))
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return -EINVAL;
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return 0;
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}
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static int __init add_clockevent(struct device_node *event_timer)
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{
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void __iomem *iobase;
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struct dw_apb_clock_event_device *ced;
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u32 irq, rate;
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int ret = 0;
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irq = irq_of_parse_and_map(event_timer, 0);
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if (irq == 0)
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panic("No IRQ for clock event timer");
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ret = timer_get_base_and_rate(event_timer, &iobase, &rate);
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if (ret)
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return ret;
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ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
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rate);
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if (!ced)
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return -EINVAL;
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dw_apb_clockevent_register(ced);
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return 0;
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}
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static void __iomem *sched_io_base;
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static u32 sched_rate;
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static int __init add_clocksource(struct device_node *source_timer)
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{
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void __iomem *iobase;
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struct dw_apb_clocksource *cs;
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u32 rate;
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int ret;
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ret = timer_get_base_and_rate(source_timer, &iobase, &rate);
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if (ret)
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return ret;
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cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
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if (!cs)
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return -EINVAL;
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dw_apb_clocksource_start(cs);
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dw_apb_clocksource_register(cs);
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/*
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* Fallback to use the clocksource as sched_clock if no separate
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* timer is found. sched_io_base then points to the current_value
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* register of the clocksource timer.
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*/
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sched_io_base = iobase + 0x04;
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sched_rate = rate;
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return 0;
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}
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static u64 notrace read_sched_clock(void)
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{
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return ~readl_relaxed(sched_io_base);
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}
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static const struct of_device_id sptimer_ids[] __initconst = {
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{ .compatible = "picochip,pc3x2-rtc" },
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{ /* Sentinel */ },
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};
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static void __init init_sched_clock(void)
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{
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struct device_node *sched_timer;
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sched_timer = of_find_matching_node(NULL, sptimer_ids);
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if (sched_timer) {
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timer_get_base_and_rate(sched_timer, &sched_io_base,
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&sched_rate);
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of_node_put(sched_timer);
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}
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sched_clock_register(read_sched_clock, 32, sched_rate);
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}
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#ifdef CONFIG_ARM
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static unsigned long dw_apb_delay_timer_read(void)
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{
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return ~readl_relaxed(sched_io_base);
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}
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static struct delay_timer dw_apb_delay_timer = {
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.read_current_timer = dw_apb_delay_timer_read,
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};
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#endif
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static int num_called;
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static int __init dw_apb_timer_init(struct device_node *timer)
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{
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int ret = 0;
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switch (num_called) {
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case 1:
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pr_debug("%s: found clocksource timer\n", __func__);
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ret = add_clocksource(timer);
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if (ret)
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return ret;
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init_sched_clock();
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#ifdef CONFIG_ARM
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dw_apb_delay_timer.freq = sched_rate;
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register_current_timer_delay(&dw_apb_delay_timer);
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#endif
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break;
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default:
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pr_debug("%s: found clockevent timer\n", __func__);
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ret = add_clockevent(timer);
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if (ret)
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return ret;
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break;
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}
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num_called++;
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return 0;
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}
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TIMER_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
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TIMER_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
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TIMER_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
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TIMER_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);
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