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2f5fbc4305
We have a problem if we use gpio-keys and configure wakeups such that we only want one edge to wake us up. AKA: wakeup-event-action = <EV_ACT_DEASSERTED>; wakeup-source; Specifically we end up with a phantom interrupt that blocks suspend if the line was already high and we want wakeups on rising edges (AKA we want the GPIO to go low and then high again before we wake up). The opposite is also problematic. Specifically, here's what's happening today: 1. Normally, gpio-keys configures to look for both edges. Due to the current workaround introduced in commitc3c0c2e18d
("pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180"), if the line was high we'd configure for falling edges. 2. At suspend time, we change to look for rising edges. 3. After qcom_pdc_gic_set_type() runs, we get a phantom interrupt. We can solve this by just clearing the phantom interrupt. NOTE: it is possible that this could cause problems for a client with very specific needs, but there's not much we can do with this hardware. As an example, let's say the interrupt signal is currently high and the client is looking for falling edges. The client now changes to look for rising edges. The client could possibly expect that if the line has a short pulse low (and back high) that it would always be detected. Specifically no matter when the pulse happened, it should either have tripped the (old) falling edge trigger or the (new) rising edge trigger. We will simply not trip it. We could narrow down the race a bit by polling our parent before changing types, but no matter what we do there will still be a period of time where we can't tell the difference between a real transition (or more than one transition) and the phantom. Fixes:f55c73aef8
("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201211141514.v4.1.I2702919afc253e2a451bebc3b701b462b2d22344@changeid
462 lines
11 KiB
C
462 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/soc/qcom/irq.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#define PDC_MAX_IRQS 168
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#define PDC_MAX_GPIO_IRQS 256
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#define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
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#define ENABLE_INTR(reg, intr) (reg | (1 << intr))
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#define IRQ_ENABLE_BANK 0x10
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#define IRQ_i_CFG 0x110
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#define PDC_NO_PARENT_IRQ ~0UL
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struct pdc_pin_region {
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u32 pin_base;
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u32 parent_base;
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u32 cnt;
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};
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static DEFINE_RAW_SPINLOCK(pdc_lock);
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static void __iomem *pdc_base;
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static struct pdc_pin_region *pdc_region;
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static int pdc_region_cnt;
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static void pdc_reg_write(int reg, u32 i, u32 val)
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{
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writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
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}
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static u32 pdc_reg_read(int reg, u32 i)
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{
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return readl_relaxed(pdc_base + reg + i * sizeof(u32));
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}
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static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which,
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bool *state)
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{
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return 0;
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return irq_chip_get_parent_state(d, which, state);
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}
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static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which,
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bool value)
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{
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return 0;
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return irq_chip_set_parent_state(d, which, value);
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}
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static void pdc_enable_intr(struct irq_data *d, bool on)
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{
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int pin_out = d->hwirq;
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u32 index, mask;
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u32 enable;
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index = pin_out / 32;
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mask = pin_out % 32;
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raw_spin_lock(&pdc_lock);
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enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
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enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
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pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
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raw_spin_unlock(&pdc_lock);
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}
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static void qcom_pdc_gic_disable(struct irq_data *d)
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{
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return;
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pdc_enable_intr(d, false);
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irq_chip_disable_parent(d);
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}
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static void qcom_pdc_gic_enable(struct irq_data *d)
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{
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return;
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pdc_enable_intr(d, true);
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irq_chip_enable_parent(d);
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}
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static void qcom_pdc_gic_mask(struct irq_data *d)
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{
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return;
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irq_chip_mask_parent(d);
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}
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static void qcom_pdc_gic_unmask(struct irq_data *d)
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{
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return;
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irq_chip_unmask_parent(d);
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}
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/*
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* GIC does not handle falling edge or active low. To allow falling edge and
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* active low interrupts to be handled at GIC, PDC has an inverter that inverts
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* falling edge into a rising edge and active low into an active high.
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* For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
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* set as per the table below.
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* Level sensitive active low LOW
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* Rising edge sensitive NOT USED
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* Falling edge sensitive LOW
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* Dual Edge sensitive NOT USED
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* Level sensitive active High HIGH
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* Falling Edge sensitive NOT USED
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* Rising edge sensitive HIGH
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* Dual Edge sensitive HIGH
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*/
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enum pdc_irq_config_bits {
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PDC_LEVEL_LOW = 0b000,
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PDC_EDGE_FALLING = 0b010,
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PDC_LEVEL_HIGH = 0b100,
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PDC_EDGE_RISING = 0b110,
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PDC_EDGE_DUAL = 0b111,
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};
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/**
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* qcom_pdc_gic_set_type: Configure PDC for the interrupt
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*
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* @d: the interrupt data
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* @type: the interrupt type
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*
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* If @type is edge triggered, forward that as Rising edge as PDC
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* takes care of converting falling edge to rising edge signal
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* If @type is level, then forward that as level high as PDC
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* takes care of converting falling edge to rising edge signal
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*/
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static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
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{
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int pin_out = d->hwirq;
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enum pdc_irq_config_bits pdc_type;
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enum pdc_irq_config_bits old_pdc_type;
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int ret;
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if (pin_out == GPIO_NO_WAKE_IRQ)
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return 0;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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pdc_type = PDC_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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pdc_type = PDC_EDGE_FALLING;
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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pdc_type = PDC_EDGE_DUAL;
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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pdc_type = PDC_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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pdc_type = PDC_LEVEL_LOW;
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type = IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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WARN_ON(1);
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return -EINVAL;
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}
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old_pdc_type = pdc_reg_read(IRQ_i_CFG, pin_out);
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pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
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ret = irq_chip_set_type_parent(d, type);
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if (ret)
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return ret;
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/*
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* When we change types the PDC can give a phantom interrupt.
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* Clear it. Specifically the phantom shows up when reconfiguring
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* polarity of interrupt without changing the state of the signal
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* but let's be consistent and clear it always.
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*
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* Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
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* interrupt will be cleared before the rest of the system sees it.
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*/
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if (old_pdc_type != pdc_type)
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irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
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return 0;
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}
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static struct irq_chip qcom_pdc_gic_chip = {
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.name = "PDC",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = qcom_pdc_gic_mask,
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.irq_unmask = qcom_pdc_gic_unmask,
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.irq_disable = qcom_pdc_gic_disable,
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.irq_enable = qcom_pdc_gic_enable,
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.irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state,
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.irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = qcom_pdc_gic_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
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.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static irq_hw_number_t get_parent_hwirq(int pin)
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{
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int i;
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struct pdc_pin_region *region;
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for (i = 0; i < pdc_region_cnt; i++) {
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region = &pdc_region[i];
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if (pin >= region->pin_base &&
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pin < region->pin_base + region->cnt)
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return (region->parent_base + pin - region->pin_base);
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}
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return PDC_NO_PARENT_IRQ;
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}
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static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
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unsigned long *hwirq, unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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return -EINVAL;
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}
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static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq, parent_hwirq;
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unsigned int type;
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int ret;
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ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&qcom_pdc_gic_chip, NULL);
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if (ret)
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return ret;
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parent_hwirq = get_parent_hwirq(hwirq);
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if (parent_hwirq == PDC_NO_PARENT_IRQ)
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return 0;
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if (type & IRQ_TYPE_EDGE_BOTH)
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type = IRQ_TYPE_EDGE_RISING;
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if (type & IRQ_TYPE_LEVEL_MASK)
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type = IRQ_TYPE_LEVEL_HIGH;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = 0;
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parent_fwspec.param[1] = parent_hwirq;
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parent_fwspec.param[2] = type;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops qcom_pdc_ops = {
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.translate = qcom_pdc_translate,
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.alloc = qcom_pdc_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq, parent_hwirq;
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unsigned int type;
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int ret;
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ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&qcom_pdc_gic_chip, NULL);
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if (ret)
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return ret;
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if (hwirq == GPIO_NO_WAKE_IRQ)
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return 0;
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parent_hwirq = get_parent_hwirq(hwirq);
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if (parent_hwirq == PDC_NO_PARENT_IRQ)
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return 0;
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if (type & IRQ_TYPE_EDGE_BOTH)
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type = IRQ_TYPE_EDGE_RISING;
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if (type & IRQ_TYPE_LEVEL_MASK)
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type = IRQ_TYPE_LEVEL_HIGH;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = 0;
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parent_fwspec.param[1] = parent_hwirq;
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parent_fwspec.param[2] = type;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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enum irq_domain_bus_token bus_token)
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{
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return bus_token == DOMAIN_BUS_WAKEUP;
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}
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static const struct irq_domain_ops qcom_pdc_gpio_ops = {
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.select = qcom_pdc_gpio_domain_select,
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.alloc = qcom_pdc_gpio_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int pdc_setup_pin_mapping(struct device_node *np)
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{
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int ret, n, i;
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u32 irq_index, reg_index, val;
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n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
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if (n <= 0 || n % 3)
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return -EINVAL;
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pdc_region_cnt = n / 3;
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pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
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if (!pdc_region) {
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pdc_region_cnt = 0;
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return -ENOMEM;
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}
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for (n = 0; n < pdc_region_cnt; n++) {
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ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
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n * 3 + 0,
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&pdc_region[n].pin_base);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
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n * 3 + 1,
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&pdc_region[n].parent_base);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
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n * 3 + 2,
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&pdc_region[n].cnt);
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if (ret)
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return ret;
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for (i = 0; i < pdc_region[n].cnt; i++) {
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reg_index = (i + pdc_region[n].pin_base) >> 5;
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irq_index = (i + pdc_region[n].pin_base) & 0x1f;
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val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
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val &= ~BIT(irq_index);
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pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
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}
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}
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return 0;
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}
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static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
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int ret;
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pdc_base = of_iomap(node, 0);
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if (!pdc_base) {
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pr_err("%pOF: unable to map PDC registers\n", node);
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return -ENXIO;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: unable to find PDC's parent domain\n", node);
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ret = -ENXIO;
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goto fail;
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}
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ret = pdc_setup_pin_mapping(node);
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if (ret) {
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pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
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goto fail;
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}
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pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
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of_fwnode_handle(node),
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&qcom_pdc_ops, NULL);
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if (!pdc_domain) {
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pr_err("%pOF: GIC domain add failed\n", node);
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ret = -ENOMEM;
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goto fail;
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}
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pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
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IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
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PDC_MAX_GPIO_IRQS,
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of_fwnode_handle(node),
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&qcom_pdc_gpio_ops, NULL);
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if (!pdc_gpio_domain) {
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pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
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ret = -ENOMEM;
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goto remove;
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}
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irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
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return 0;
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remove:
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irq_domain_remove(pdc_domain);
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fail:
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kfree(pdc_region);
|
|
iounmap(pdc_base);
|
|
return ret;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
|