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![Dan Carpenter](/assets/img/avatar_default.png)
This line was accidentally indented too far. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Mark Brown <broonie@kernel.org>
957 lines
25 KiB
C
957 lines
25 KiB
C
/*
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* STM32 ALSA SoC Digital Audio Interface (SAI) driver.
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
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*
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* License terms: GPL V2.0.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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* details.
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*/
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include "stm32_sai.h"
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#define SAI_FREE_PROTOCOL 0x0
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#define SAI_SLOT_SIZE_AUTO 0x0
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#define SAI_SLOT_SIZE_16 0x1
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#define SAI_SLOT_SIZE_32 0x2
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#define SAI_DATASIZE_8 0x2
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#define SAI_DATASIZE_10 0x3
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#define SAI_DATASIZE_16 0x4
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#define SAI_DATASIZE_20 0x5
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#define SAI_DATASIZE_24 0x6
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#define SAI_DATASIZE_32 0x7
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#define STM_SAI_FIFO_SIZE 8
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#define STM_SAI_DAI_NAME_SIZE 15
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#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
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#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
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#define STM_SAI_A_ID 0x0
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#define STM_SAI_B_ID 0x1
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#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
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#define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
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#define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
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/**
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* struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
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* @pdev: device data pointer
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* @regmap: SAI register map pointer
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* @regmap_config: SAI sub block register map configuration pointer
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* @dma_params: dma configuration data for rx or tx channel
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* @cpu_dai_drv: DAI driver data pointer
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* @cpu_dai: DAI runtime data pointer
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* @substream: PCM substream data pointer
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* @pdata: SAI block parent data pointer
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* @sai_ck: kernel clock feeding the SAI clock generator
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* @phys_addr: SAI registers physical base address
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* @mclk_rate: SAI block master clock frequency (Hz). set at init
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* @id: SAI sub block id corresponding to sub-block A or B
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* @dir: SAI block direction (playback or capture). set at init
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* @master: SAI block mode flag. (true=master, false=slave) set at init
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* @fmt: SAI block format. relevant only for custom protocols. set at init
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* @sync: SAI block synchronization mode. (none, internal or external)
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* @fs_length: frame synchronization length. depends on protocol settings
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* @slots: rx or tx slot number
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* @slot_width: rx or tx slot width in bits
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* @slot_mask: rx or tx active slots mask. set at init or at runtime
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* @data_size: PCM data width. corresponds to PCM substream width.
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*/
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struct stm32_sai_sub_data {
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struct platform_device *pdev;
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struct regmap *regmap;
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const struct regmap_config *regmap_config;
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struct snd_dmaengine_dai_dma_data dma_params;
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struct snd_soc_dai_driver *cpu_dai_drv;
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struct snd_soc_dai *cpu_dai;
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struct snd_pcm_substream *substream;
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struct stm32_sai_data *pdata;
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struct clk *sai_ck;
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dma_addr_t phys_addr;
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unsigned int mclk_rate;
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unsigned int id;
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int dir;
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bool master;
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int fmt;
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int sync;
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int fs_length;
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int slots;
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int slot_width;
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int slot_mask;
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int data_size;
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};
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enum stm32_sai_fifo_th {
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STM_SAI_FIFO_TH_EMPTY,
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STM_SAI_FIFO_TH_QUARTER,
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STM_SAI_FIFO_TH_HALF,
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STM_SAI_FIFO_TH_3_QUARTER,
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STM_SAI_FIFO_TH_FULL,
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};
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static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case STM_SAI_CR1_REGX:
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case STM_SAI_CR2_REGX:
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case STM_SAI_FRCR_REGX:
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case STM_SAI_SLOTR_REGX:
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case STM_SAI_IMR_REGX:
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case STM_SAI_SR_REGX:
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case STM_SAI_CLRFR_REGX:
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case STM_SAI_DR_REGX:
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case STM_SAI_PDMCR_REGX:
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case STM_SAI_PDMLY_REGX:
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return true;
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default:
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return false;
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}
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}
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static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case STM_SAI_DR_REGX:
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return true;
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default:
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return false;
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}
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}
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static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case STM_SAI_CR1_REGX:
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case STM_SAI_CR2_REGX:
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case STM_SAI_FRCR_REGX:
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case STM_SAI_SLOTR_REGX:
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case STM_SAI_IMR_REGX:
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case STM_SAI_SR_REGX:
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case STM_SAI_CLRFR_REGX:
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case STM_SAI_DR_REGX:
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case STM_SAI_PDMCR_REGX:
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case STM_SAI_PDMLY_REGX:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = STM_SAI_DR_REGX,
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.readable_reg = stm32_sai_sub_readable_reg,
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.volatile_reg = stm32_sai_sub_volatile_reg,
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.writeable_reg = stm32_sai_sub_writeable_reg,
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.fast_io = true,
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};
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static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = STM_SAI_PDMLY_REGX,
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.readable_reg = stm32_sai_sub_readable_reg,
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.volatile_reg = stm32_sai_sub_volatile_reg,
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.writeable_reg = stm32_sai_sub_writeable_reg,
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.fast_io = true,
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};
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static irqreturn_t stm32_sai_isr(int irq, void *devid)
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{
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struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
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struct snd_pcm_substream *substream = sai->substream;
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struct platform_device *pdev = sai->pdev;
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unsigned int sr, imr, flags;
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snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
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regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
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regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
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flags = sr & imr;
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if (!flags)
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return IRQ_NONE;
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regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
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SAI_XCLRFR_MASK);
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if (flags & SAI_XIMR_OVRUDRIE) {
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dev_err(&pdev->dev, "IRQ %s\n",
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STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
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status = SNDRV_PCM_STATE_XRUN;
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}
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if (flags & SAI_XIMR_MUTEDETIE)
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dev_dbg(&pdev->dev, "IRQ mute detected\n");
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if (flags & SAI_XIMR_WCKCFGIE) {
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dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
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status = SNDRV_PCM_STATE_DISCONNECTED;
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}
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if (flags & SAI_XIMR_CNRDYIE)
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dev_err(&pdev->dev, "IRQ Codec not ready\n");
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if (flags & SAI_XIMR_AFSDETIE) {
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dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
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status = SNDRV_PCM_STATE_XRUN;
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}
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if (flags & SAI_XIMR_LFSDETIE) {
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dev_err(&pdev->dev, "IRQ Late frame synchro\n");
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status = SNDRV_PCM_STATE_XRUN;
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}
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if (status != SNDRV_PCM_STATE_RUNNING) {
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snd_pcm_stream_lock(substream);
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snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
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snd_pcm_stream_unlock(substream);
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}
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return IRQ_HANDLED;
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}
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static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int ret;
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if ((dir == SND_SOC_CLOCK_OUT) && sai->master) {
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ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
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SAI_XCR1_NODIV,
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(unsigned int)~SAI_XCR1_NODIV);
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if (ret < 0)
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return ret;
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sai->mclk_rate = freq;
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dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
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}
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return 0;
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}
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static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
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u32 rx_mask, int slots, int slot_width)
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int slotr, slotr_mask, slot_size;
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dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
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tx_mask, rx_mask, slots, slot_width);
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switch (slot_width) {
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case 16:
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slot_size = SAI_SLOT_SIZE_16;
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break;
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case 32:
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slot_size = SAI_SLOT_SIZE_32;
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break;
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default:
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slot_size = SAI_SLOT_SIZE_AUTO;
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break;
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}
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slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
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SAI_XSLOTR_NBSLOT_SET(slots - 1);
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slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
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/* tx/rx mask set in machine init, if slot number defined in DT */
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if (STM_SAI_IS_PLAYBACK(sai)) {
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sai->slot_mask = tx_mask;
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slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
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}
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if (STM_SAI_IS_CAPTURE(sai)) {
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sai->slot_mask = rx_mask;
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slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
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}
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slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
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regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
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sai->slot_width = slot_width;
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sai->slots = slots;
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return 0;
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}
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static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int cr1 = 0, frcr = 0;
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int cr1_mask = 0, frcr_mask = 0;
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int ret;
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dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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/* SCK active high for all protocols */
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case SND_SOC_DAIFMT_I2S:
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cr1 |= SAI_XCR1_CKSTR;
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frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
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break;
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/* Left justified */
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case SND_SOC_DAIFMT_MSB:
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frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
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break;
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/* Right justified */
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case SND_SOC_DAIFMT_LSB:
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frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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frcr |= SAI_XFRCR_FSPOL;
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break;
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default:
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dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
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fmt & SND_SOC_DAIFMT_FORMAT_MASK);
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return -EINVAL;
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}
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cr1_mask |= SAI_XCR1_PRTCFG_MASK | SAI_XCR1_CKSTR;
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frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
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SAI_XFRCR_FSDEF;
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/* DAI clock strobing. Invert setting previously set */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_IB_NF:
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cr1 ^= SAI_XCR1_CKSTR;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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frcr ^= SAI_XFRCR_FSPOL;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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/* Invert fs & sck */
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cr1 ^= SAI_XCR1_CKSTR;
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frcr ^= SAI_XFRCR_FSPOL;
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break;
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default:
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dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
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fmt & SND_SOC_DAIFMT_INV_MASK);
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return -EINVAL;
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}
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cr1_mask |= SAI_XCR1_CKSTR;
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frcr_mask |= SAI_XFRCR_FSPOL;
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regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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/* codec is master */
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cr1 |= SAI_XCR1_SLAVE;
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sai->master = false;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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sai->master = true;
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break;
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default:
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dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
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fmt & SND_SOC_DAIFMT_MASTER_MASK);
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return -EINVAL;
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}
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cr1_mask |= SAI_XCR1_SLAVE;
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/* do not generate master by default */
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cr1 |= SAI_XCR1_NODIV;
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cr1_mask |= SAI_XCR1_NODIV;
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ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
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if (ret < 0) {
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dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
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return ret;
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}
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sai->fmt = fmt;
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return 0;
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}
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static int stm32_sai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int imr, cr2, ret;
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sai->substream = substream;
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ret = clk_prepare_enable(sai->sai_ck);
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if (ret < 0) {
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dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
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return ret;
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}
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/* Enable ITs */
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regmap_update_bits(sai->regmap, STM_SAI_SR_REGX,
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SAI_XSR_MASK, (unsigned int)~SAI_XSR_MASK);
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regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
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SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
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imr = SAI_XIMR_OVRUDRIE;
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if (STM_SAI_IS_CAPTURE(sai)) {
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regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
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if (cr2 & SAI_XCR2_MUTECNT_MASK)
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imr |= SAI_XIMR_MUTEDETIE;
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}
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if (sai->master)
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imr |= SAI_XIMR_WCKCFGIE;
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else
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imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
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regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
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SAI_XIMR_MASK, imr);
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return 0;
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}
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static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int cr1, cr1_mask, ret;
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int fth = STM_SAI_FIFO_TH_HALF;
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/* FIFO config */
|
|
regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX,
|
|
SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
|
|
SAI_XCR2_FFLUSH | SAI_XCR2_FTH_SET(fth));
|
|
|
|
/* Mode, data format and channel config */
|
|
cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
|
|
switch (params_format(params)) {
|
|
case SNDRV_PCM_FORMAT_S8:
|
|
cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_8);
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_16);
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_32);
|
|
break;
|
|
default:
|
|
dev_err(cpu_dai->dev, "Data format not supported");
|
|
return -EINVAL;
|
|
}
|
|
cr1_mask = SAI_XCR1_DS_MASK | SAI_XCR1_PRTCFG_MASK;
|
|
|
|
cr1_mask |= SAI_XCR1_RX_TX;
|
|
if (STM_SAI_IS_CAPTURE(sai))
|
|
cr1 |= SAI_XCR1_RX_TX;
|
|
|
|
cr1_mask |= SAI_XCR1_MONO;
|
|
if ((sai->slots == 2) && (params_channels(params) == 1))
|
|
cr1 |= SAI_XCR1_MONO;
|
|
|
|
ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
|
|
if (ret < 0) {
|
|
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
|
|
return ret;
|
|
}
|
|
|
|
/* DMA config */
|
|
sai->dma_params.maxburst = STM_SAI_FIFO_SIZE * fth / sizeof(u32);
|
|
snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)&sai->dma_params);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
|
int slotr, slot_sz;
|
|
|
|
regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
|
|
|
|
/*
|
|
* If SLOTSZ is set to auto in SLOTR, align slot width on data size
|
|
* By default slot width = data size, if not forced from DT
|
|
*/
|
|
slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
|
|
if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
|
|
sai->slot_width = sai->data_size;
|
|
|
|
if (sai->slot_width < sai->data_size) {
|
|
dev_err(cpu_dai->dev,
|
|
"Data size %d larger than slot width\n",
|
|
sai->data_size);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Slot number is set to 2, if not specified in DT */
|
|
if (!sai->slots)
|
|
sai->slots = 2;
|
|
|
|
/* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
|
|
regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
|
|
SAI_XSLOTR_NBSLOT_MASK,
|
|
SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
|
|
|
|
/* Set default slots mask if not already set from DT */
|
|
if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
|
|
sai->slot_mask = (1 << sai->slots) - 1;
|
|
regmap_update_bits(sai->regmap,
|
|
STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
|
|
SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
|
|
}
|
|
|
|
dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
|
|
sai->slots, sai->slot_width);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
|
int fs_active, offset, format;
|
|
int frcr, frcr_mask;
|
|
|
|
format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
|
|
sai->fs_length = sai->slot_width * sai->slots;
|
|
|
|
fs_active = sai->fs_length / 2;
|
|
if ((format == SND_SOC_DAIFMT_DSP_A) ||
|
|
(format == SND_SOC_DAIFMT_DSP_B))
|
|
fs_active = 1;
|
|
|
|
frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
|
|
frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
|
|
frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
|
|
|
|
dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
|
|
sai->fs_length, fs_active);
|
|
|
|
regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
|
|
|
|
if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
|
|
offset = sai->slot_width - sai->data_size;
|
|
|
|
regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
|
|
SAI_XSLOTR_FBOFF_MASK,
|
|
SAI_XSLOTR_FBOFF_SET(offset));
|
|
}
|
|
}
|
|
|
|
static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
|
|
struct snd_pcm_hw_params *params)
|
|
{
|
|
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
|
int cr1, mask, div = 0;
|
|
int sai_clk_rate, mclk_ratio, den, ret;
|
|
int version = sai->pdata->conf->version;
|
|
|
|
if (!sai->mclk_rate) {
|
|
dev_err(cpu_dai->dev, "Mclk rate is null\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!(params_rate(params) % 11025))
|
|
clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
|
|
else
|
|
clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
|
|
sai_clk_rate = clk_get_rate(sai->sai_ck);
|
|
|
|
if (STM_SAI_IS_F4(sai->pdata)) {
|
|
/*
|
|
* mclk_rate = 256 * fs
|
|
* MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
|
|
* MCKDIV = sai_ck / (2 * mclk_rate) otherwise
|
|
*/
|
|
if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
|
|
div = DIV_ROUND_CLOSEST(sai_clk_rate,
|
|
2 * sai->mclk_rate);
|
|
} else {
|
|
/*
|
|
* TDM mode :
|
|
* mclk on
|
|
* MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
|
|
* MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
|
|
* mclk off
|
|
* MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
|
|
* Note: NOMCK/NODIV correspond to same bit.
|
|
*/
|
|
if (sai->mclk_rate) {
|
|
mclk_ratio = sai->mclk_rate / params_rate(params);
|
|
if (mclk_ratio != 256) {
|
|
if (mclk_ratio == 512) {
|
|
mask = SAI_XCR1_OSR;
|
|
cr1 = SAI_XCR1_OSR;
|
|
} else {
|
|
dev_err(cpu_dai->dev,
|
|
"Wrong mclk ratio %d\n",
|
|
mclk_ratio);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
div = DIV_ROUND_CLOSEST(sai_clk_rate, sai->mclk_rate);
|
|
} else {
|
|
/* mclk-fs not set, master clock not active. NOMCK=1 */
|
|
den = sai->fs_length * params_rate(params);
|
|
div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
|
|
}
|
|
}
|
|
|
|
if (div > SAI_XCR1_MCKDIV_MAX(version)) {
|
|
dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
|
|
return -EINVAL;
|
|
}
|
|
dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
|
|
|
|
mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
|
|
cr1 = SAI_XCR1_MCKDIV_SET(div);
|
|
ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
|
|
if (ret < 0) {
|
|
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
|
int ret;
|
|
|
|
sai->data_size = params_width(params);
|
|
|
|
ret = stm32_sai_set_slots(cpu_dai);
|
|
if (ret < 0)
|
|
return ret;
|
|
stm32_sai_set_frame(cpu_dai);
|
|
|
|
ret = stm32_sai_set_config(cpu_dai, substream, params);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (sai->master)
|
|
ret = stm32_sai_configure_clock(cpu_dai, params);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
|
int ret;
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
|
|
|
|
regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
|
|
SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
|
|
|
|
/* Enable SAI */
|
|
ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
|
|
SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
|
|
if (ret < 0)
|
|
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
|
|
|
|
regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
|
|
SAI_XCR1_SAIEN,
|
|
(unsigned int)~SAI_XCR1_SAIEN);
|
|
|
|
ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
|
|
SAI_XCR1_DMAEN,
|
|
(unsigned int)~SAI_XCR1_DMAEN);
|
|
if (ret < 0)
|
|
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
|
|
|
regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
|
|
|
|
regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
|
|
SAI_XCR1_NODIV);
|
|
|
|
clk_disable_unprepare(sai->sai_ck);
|
|
sai->substream = NULL;
|
|
}
|
|
|
|
static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
|
|
|
|
sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
|
|
sai->dma_params.maxburst = 1;
|
|
/* Buswidth will be set by framework at runtime */
|
|
sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
|
|
|
if (STM_SAI_IS_PLAYBACK(sai))
|
|
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
|
|
else
|
|
snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
|
|
.set_sysclk = stm32_sai_set_sysclk,
|
|
.set_fmt = stm32_sai_set_dai_fmt,
|
|
.set_tdm_slot = stm32_sai_set_dai_tdm_slot,
|
|
.startup = stm32_sai_startup,
|
|
.hw_params = stm32_sai_hw_params,
|
|
.trigger = stm32_sai_trigger,
|
|
.shutdown = stm32_sai_shutdown,
|
|
};
|
|
|
|
static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
|
|
.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
|
|
.buffer_bytes_max = 8 * PAGE_SIZE,
|
|
.period_bytes_min = 1024, /* 5ms at 48kHz */
|
|
.period_bytes_max = PAGE_SIZE,
|
|
.periods_min = 2,
|
|
.periods_max = 8,
|
|
};
|
|
|
|
static struct snd_soc_dai_driver stm32_sai_playback_dai[] = {
|
|
{
|
|
.probe = stm32_sai_dai_probe,
|
|
.id = 1, /* avoid call to fmt_single_name() */
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rate_min = 8000,
|
|
.rate_max = 192000,
|
|
.rates = SNDRV_PCM_RATE_CONTINUOUS,
|
|
/* DMA does not support 24 bits transfers */
|
|
.formats =
|
|
SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.ops = &stm32_sai_pcm_dai_ops,
|
|
}
|
|
};
|
|
|
|
static struct snd_soc_dai_driver stm32_sai_capture_dai[] = {
|
|
{
|
|
.probe = stm32_sai_dai_probe,
|
|
.id = 1, /* avoid call to fmt_single_name() */
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rate_min = 8000,
|
|
.rate_max = 192000,
|
|
.rates = SNDRV_PCM_RATE_CONTINUOUS,
|
|
/* DMA does not support 24 bits transfers */
|
|
.formats =
|
|
SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.ops = &stm32_sai_pcm_dai_ops,
|
|
}
|
|
};
|
|
|
|
static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
|
|
.pcm_hardware = &stm32_sai_pcm_hw,
|
|
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver stm32_component = {
|
|
.name = "stm32-sai",
|
|
};
|
|
|
|
static const struct of_device_id stm32_sai_sub_ids[] = {
|
|
{ .compatible = "st,stm32-sai-sub-a",
|
|
.data = (void *)STM_SAI_A_ID},
|
|
{ .compatible = "st,stm32-sai-sub-b",
|
|
.data = (void *)STM_SAI_B_ID},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
|
|
|
|
static int stm32_sai_sub_parse_of(struct platform_device *pdev,
|
|
struct stm32_sai_sub_data *sai)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
sai->phys_addr = res->start;
|
|
|
|
sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
|
|
/* Note: PDM registers not available for H7 sub-block B */
|
|
if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
|
|
sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
|
|
|
|
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
|
|
base, sai->regmap_config);
|
|
if (IS_ERR(sai->regmap)) {
|
|
dev_err(&pdev->dev, "Failed to initialize MMIO\n");
|
|
return PTR_ERR(sai->regmap);
|
|
}
|
|
|
|
/* Get direction property */
|
|
if (of_property_match_string(np, "dma-names", "tx") >= 0) {
|
|
sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
|
|
} else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
|
|
sai->dir = SNDRV_PCM_STREAM_CAPTURE;
|
|
} else {
|
|
dev_err(&pdev->dev, "Unsupported direction\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
|
|
if (IS_ERR(sai->sai_ck)) {
|
|
dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
|
|
return PTR_ERR(sai->sai_ck);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_sai_sub_dais_init(struct platform_device *pdev,
|
|
struct stm32_sai_sub_data *sai)
|
|
{
|
|
sai->cpu_dai_drv = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct snd_soc_dai_driver),
|
|
GFP_KERNEL);
|
|
if (!sai->cpu_dai_drv)
|
|
return -ENOMEM;
|
|
|
|
sai->cpu_dai_drv->name = dev_name(&pdev->dev);
|
|
if (STM_SAI_IS_PLAYBACK(sai)) {
|
|
memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai,
|
|
sizeof(stm32_sai_playback_dai));
|
|
sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name;
|
|
} else {
|
|
memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai,
|
|
sizeof(stm32_sai_capture_dai));
|
|
sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_sai_sub_probe(struct platform_device *pdev)
|
|
{
|
|
struct stm32_sai_sub_data *sai;
|
|
const struct of_device_id *of_id;
|
|
int ret;
|
|
|
|
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
|
|
if (!sai)
|
|
return -ENOMEM;
|
|
|
|
of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
|
|
if (!of_id)
|
|
return -EINVAL;
|
|
sai->id = (uintptr_t)of_id->data;
|
|
|
|
sai->pdev = pdev;
|
|
platform_set_drvdata(pdev, sai);
|
|
|
|
sai->pdata = dev_get_drvdata(pdev->dev.parent);
|
|
if (!sai->pdata) {
|
|
dev_err(&pdev->dev, "Parent device data not available\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = stm32_sai_sub_parse_of(pdev, sai);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = stm32_sai_sub_dais_init(pdev, sai);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
|
|
IRQF_SHARED, dev_name(&pdev->dev), sai);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
|
|
sai->cpu_dai_drv, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
|
|
&stm32_sai_pcm_config, 0);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Could not register pcm dma\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver stm32_sai_sub_driver = {
|
|
.driver = {
|
|
.name = "st,stm32-sai-sub",
|
|
.of_match_table = stm32_sai_sub_ids,
|
|
},
|
|
.probe = stm32_sai_sub_probe,
|
|
};
|
|
|
|
module_platform_driver(stm32_sai_sub_driver);
|
|
|
|
MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
|
|
MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
|
|
MODULE_ALIAS("platform:st,stm32-sai-sub");
|
|
MODULE_LICENSE("GPL v2");
|