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b59049720d
This allows additional registers to be accessed by the guest in PR-mode KVM without trapping. SPRG4-7 are readable from userspace. On booke, KVM will sync these registers when it enters the guest, so that accesses from guest userspace will work. The guest kernel, OTOH, must consistently use either the real registers or the shared area between exits. This also applies to the already-paravirted SPRG3. On non-booke, it's not clear to what extent SPRG4-7 are supported (they're not architected for book3s, but exist on at least some classic chips). They are copied in the get/set regs ioctls, but I do not see any non-booke emulation. I also do not see any syncing with real registers (in PR-mode) including the user-readable SPRG3. This patch should not make that situation any worse. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
174 lines
4.7 KiB
C
174 lines
4.7 KiB
C
/*
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* Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, yu.liu@freescale.com
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*
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* Description:
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* This file is based on arch/powerpc/kvm/44x_tlb.h,
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* by Hollis Blanchard <hollisb@us.ibm.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef __KVM_E500_TLB_H__
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#define __KVM_E500_TLB_H__
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#include <linux/kvm_host.h>
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#include <asm/mmu-book3e.h>
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#include <asm/tlb.h>
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#include <asm/kvm_e500.h>
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/* This geometry is the legacy default -- can be overridden by userspace */
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#define KVM_E500_TLB0_WAY_SIZE 128
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#define KVM_E500_TLB0_WAY_NUM 2
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#define KVM_E500_TLB0_SIZE (KVM_E500_TLB0_WAY_SIZE * KVM_E500_TLB0_WAY_NUM)
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#define KVM_E500_TLB1_SIZE 16
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#define index_of(tlbsel, esel) (((tlbsel) << 16) | ((esel) & 0xFFFF))
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#define tlbsel_of(index) ((index) >> 16)
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#define esel_of(index) ((index) & 0xFFFF)
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#define E500_TLB_USER_PERM_MASK (MAS3_UX|MAS3_UR|MAS3_UW)
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#define E500_TLB_SUPER_PERM_MASK (MAS3_SX|MAS3_SR|MAS3_SW)
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#define MAS2_ATTRIB_MASK \
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(MAS2_X0 | MAS2_X1)
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#define MAS3_ATTRIB_MASK \
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(MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3 \
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| E500_TLB_USER_PERM_MASK | E500_TLB_SUPER_PERM_MASK)
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extern void kvmppc_dump_tlbs(struct kvm_vcpu *);
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extern int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *, ulong);
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extern int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *);
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extern int kvmppc_e500_emul_tlbre(struct kvm_vcpu *);
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extern int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *, int, int);
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extern int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *, int);
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extern int kvmppc_e500_tlb_search(struct kvm_vcpu *, gva_t, unsigned int, int);
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extern void kvmppc_e500_tlb_put(struct kvm_vcpu *);
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extern void kvmppc_e500_tlb_load(struct kvm_vcpu *, int);
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extern int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *);
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extern void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *);
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extern void kvmppc_e500_tlb_setup(struct kvmppc_vcpu_e500 *);
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extern void kvmppc_e500_recalc_shadow_pid(struct kvmppc_vcpu_e500 *);
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/* TLB helper functions */
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static inline unsigned int
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get_tlb_size(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return (tlbe->mas1 >> 7) & 0x1f;
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}
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static inline gva_t get_tlb_eaddr(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return tlbe->mas2 & 0xfffff000;
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}
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static inline u64 get_tlb_bytes(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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unsigned int pgsize = get_tlb_size(tlbe);
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return 1ULL << 10 << pgsize;
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}
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static inline gva_t get_tlb_end(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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u64 bytes = get_tlb_bytes(tlbe);
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return get_tlb_eaddr(tlbe) + bytes - 1;
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}
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static inline u64 get_tlb_raddr(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return tlbe->mas7_3 & ~0xfffULL;
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}
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static inline unsigned int
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get_tlb_tid(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return (tlbe->mas1 >> 16) & 0xff;
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}
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static inline unsigned int
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get_tlb_ts(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return (tlbe->mas1 >> 12) & 0x1;
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}
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static inline unsigned int
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get_tlb_v(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return (tlbe->mas1 >> 31) & 0x1;
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}
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static inline unsigned int
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get_tlb_iprot(const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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return (tlbe->mas1 >> 30) & 0x1;
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}
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static inline unsigned int get_cur_pid(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.pid & 0xff;
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}
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static inline unsigned int get_cur_as(struct kvm_vcpu *vcpu)
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{
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return !!(vcpu->arch.shared->msr & (MSR_IS | MSR_DS));
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}
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static inline unsigned int get_cur_pr(struct kvm_vcpu *vcpu)
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{
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return !!(vcpu->arch.shared->msr & MSR_PR);
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}
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static inline unsigned int get_cur_spid(const struct kvm_vcpu *vcpu)
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{
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return (vcpu->arch.shared->mas6 >> 16) & 0xff;
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}
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static inline unsigned int get_cur_sas(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.shared->mas6 & 0x1;
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}
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static inline unsigned int get_tlb_tlbsel(const struct kvm_vcpu *vcpu)
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{
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/*
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* Manual says that tlbsel has 2 bits wide.
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* Since we only have two TLBs, only lower bit is used.
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*/
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return (vcpu->arch.shared->mas0 >> 28) & 0x1;
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}
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static inline unsigned int get_tlb_nv_bit(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.shared->mas0 & 0xfff;
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}
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static inline unsigned int get_tlb_esel_bit(const struct kvm_vcpu *vcpu)
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{
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return (vcpu->arch.shared->mas0 >> 16) & 0xfff;
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}
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static inline int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
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const struct kvm_book3e_206_tlb_entry *tlbe)
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{
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gpa_t gpa;
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if (!get_tlb_v(tlbe))
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return 0;
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/* Does it match current guest AS? */
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/* XXX what about IS != DS? */
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if (get_tlb_ts(tlbe) != !!(vcpu->arch.shared->msr & MSR_IS))
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return 0;
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gpa = get_tlb_raddr(tlbe);
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if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
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/* Mapping is not for RAM. */
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return 0;
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return 1;
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}
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#endif /* __KVM_E500_TLB_H__ */
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