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![Chris Wilson](/assets/img/avatar_default.png)
If we hit the error path, we have never called drm_encoder_init() and so
have nothing to cleanup. Doing so hits a null dereference:
[ 10.066261] BUG: unable to handle kernel NULL pointer dereference at 00000104
[ 10.066273] IP: [<c16054b4>] mutex_lock+0xa/0x15
[ 10.066287] *pde = 00000000
[ 10.066295] Oops: 0002 [#1]
[ 10.066302] Modules linked in: i915(+) video i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm iTCO_wdt iTCO_vendor_support ppdev evdev snd_intel8x0 snd_ac97_codec ac97_bus psmouse snd_pcm snd_timer snd pcspkr uhci_hcd ehci_pci soundcore sr_mod ehci_hcd serio_raw i2c_i801 usbcore i2c_smbus cdrom lpc_ich mfd_core rng_core e100 mii floppy parport_pc parport acpi_cpufreq button processor usb_common eeprom lm85 hwmon_vid autofs4
[ 10.066378] CPU: 0 PID: 132 Comm: systemd-udevd Not tainted 4.8.0-rc3-00013-gef0e1ea #34
[ 10.066389] Hardware name: MicroLink /D865GLC , BIOS BF86510A.86A.0077.P25.0508040031 08/04/2005
[ 10.066401] task: f62db800 task.stack: f5970000
[ 10.066409] EIP: 0060:[<c16054b4>] EFLAGS: 00010286 CPU: 0
[ 10.066417] EIP is at mutex_lock+0xa/0x15
[ 10.066424] EAX: 00000104 EBX: 00000104 ECX: 00000000 EDX: 80000000
[ 10.066432] ESI: 00000000 EDI: 00000104 EBP: f5be8000 ESP: f5971b58
[ 10.066439] DS: 007b ES: 007b FS: 0000 GS: 00e0 SS: 0068
[ 10.066446] CR0: 80050033 CR2: 00000104 CR3: 35945000 CR4: 000006d0
[ 10.066453] Stack:
[ 10.066459] f503d740 f824dddf 00000000 f61170c0 f61170c0 f82371ae f850f40e 00000001
[ 10.066476] f61170c0 f5971bcc f5be8000 f9c2d401 00000001 f8236fcc 00000001 00000000
[ 10.066491] f5144014 f5be8104 00000008 f9c5267c 00000007 f61170c0 f5144400 f9c4ff00
[ 10.066507] Call Trace:
[ 10.066526] [<f824dddf>] ? drm_modeset_lock_all+0x27/0xb3 [drm]
[ 10.066545] [<f82371ae>] ? drm_encoder_cleanup+0x1a/0x132 [drm]
[ 10.066559] [<f850f40e>] ? drm_atomic_helper_connector_reset+0x3f/0x5c [drm_kms_helper]
[ 10.066644] [<f9c2d401>] ? intel_dvo_init+0x569/0x788 [i915]
[ 10.066663] [<f8236fcc>] ? drm_encoder_init+0x43/0x20b [drm]
[ 10.066734] [<f9bf1fce>] ? intel_modeset_init+0x1436/0x17dd [i915]
[ 10.066791] [<f9b37636>] ? i915_driver_load+0x85a/0x15d3 [i915]
[ 10.066846] [<f9b3603d>] ? i915_driver_open+0x5/0x5 [i915]
[ 10.066857] [<c14af4d0>] ? firmware_map_add_entry.part.2+0xc/0xc
[ 10.066868] [<c1343daf>] ? pci_device_probe+0x8e/0x11c
[ 10.066878] [<c140cec8>] ? driver_probe_device+0x1db/0x62e
[ 10.066888] [<c120c010>] ? kernfs_new_node+0x29/0x9c
[ 10.066897] [<c13438e0>] ? pci_match_device+0xd9/0x161
[ 10.066905] [<c120c48b>] ? kernfs_create_dir_ns+0x42/0x88
[ 10.066914] [<c140d401>] ? __driver_attach+0xe6/0x11b
[ 10.066924] [<c1303b13>] ? kobject_add_internal+0x1bb/0x44f
[ 10.066933] [<c140d31b>] ? driver_probe_device+0x62e/0x62e
[ 10.066941] [<c140a2d2>] ? bus_for_each_dev+0x46/0x7f
[ 10.066950] [<c140c502>] ? driver_attach+0x1a/0x34
[ 10.066958] [<c140d31b>] ? driver_probe_device+0x62e/0x62e
[ 10.066966] [<c140b758>] ? bus_add_driver+0x217/0x32a
[ 10.066975] [<f8403000>] ? 0xf8403000
[ 10.066982] [<c140de27>] ? driver_register+0x5f/0x108
[ 10.066991] [<c1000493>] ? do_one_initcall+0x49/0x1f6
[ 10.067000] [<c1082299>] ? pick_next_task_fair+0x14b/0x2a3
[ 10.067008] [<c1603c8d>] ? __schedule+0x15c/0x4fe
[ 10.067016] [<c1604104>] ? preempt_schedule_common+0x19/0x3c
[ 10.067027] [<c11051de>] ? do_init_module+0x17/0x230
[ 10.067035] [<c1604139>] ? _cond_resched+0x12/0x1a
[ 10.067044] [<c116f9aa>] ? kmem_cache_alloc+0x8f/0x11f
[ 10.067052] [<c11051de>] ? do_init_module+0x17/0x230
[ 10.067060] [<c11703dd>] ? kfree+0x137/0x203
[ 10.067068] [<c110523d>] ? do_init_module+0x76/0x230
[ 10.067078] [<c10cadf3>] ? load_module+0x2a39/0x333f
[ 10.067087] [<c10cb8b2>] ? SyS_finit_module+0x96/0xd5
[ 10.067096] [<c1132231>] ? vm_mmap_pgoff+0x79/0xa0
[ 10.067105] [<c1001e96>] ? do_fast_syscall_32+0xb5/0x1b0
[ 10.067114] [<c16086a6>] ? sysenter_past_esp+0x47/0x75
[ 10.067121] Code: c8 f7 76 c1 e8 8e cc d2 ff e9 45 fe ff ff 66 90 66 90 66 90 66 90 90 ff 00 7f 05 e8 4e 0c 00 00 c3 53 89 c3 e8 75 ec ff ff 89 d8 <ff> 08 79 05 e8 fa 0a 00 00 5b c3 53 89 c3 85 c0 74 1b 8b 03 83
[ 10.067180] EIP: [<c16054b4>] mutex_lock+0xa/0x15 SS:ESP 0068:f5971b58
[ 10.067190] CR2: 0000000000000104
[ 10.067222] ---[ end trace 049f1f09da45a856 ]---
Reported-by: Meelis Roos <mroos@linux.ee>
Fixes: 580d8ed522
("drm/i915: Give encoders useful names")
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160823092558.14931-1-chris@chris-wilson.co.uk
564 lines
16 KiB
C
564 lines
16 KiB
C
/*
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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2007 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*/
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "dvo.h"
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#define SIL164_ADDR 0x38
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#define CH7xxx_ADDR 0x76
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#define TFP410_ADDR 0x38
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#define NS2501_ADDR 0x38
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static const struct intel_dvo_device intel_dvo_devices[] = {
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{
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.type = INTEL_DVO_CHIP_TMDS,
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.name = "sil164",
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.dvo_reg = DVOC,
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.dvo_srcdim_reg = DVOC_SRCDIM,
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.slave_addr = SIL164_ADDR,
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.dev_ops = &sil164_ops,
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},
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{
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.type = INTEL_DVO_CHIP_TMDS,
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.name = "ch7xxx",
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.dvo_reg = DVOC,
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.dvo_srcdim_reg = DVOC_SRCDIM,
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.slave_addr = CH7xxx_ADDR,
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.dev_ops = &ch7xxx_ops,
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},
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{
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.type = INTEL_DVO_CHIP_TMDS,
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.name = "ch7xxx",
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.dvo_reg = DVOC,
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.dvo_srcdim_reg = DVOC_SRCDIM,
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.slave_addr = 0x75, /* For some ch7010 */
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.dev_ops = &ch7xxx_ops,
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},
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{
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.type = INTEL_DVO_CHIP_LVDS,
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.name = "ivch",
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.dvo_reg = DVOA,
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.dvo_srcdim_reg = DVOA_SRCDIM,
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.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
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.dev_ops = &ivch_ops,
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},
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{
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.type = INTEL_DVO_CHIP_TMDS,
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.name = "tfp410",
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.dvo_reg = DVOC,
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.dvo_srcdim_reg = DVOC_SRCDIM,
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.slave_addr = TFP410_ADDR,
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.dev_ops = &tfp410_ops,
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},
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{
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.type = INTEL_DVO_CHIP_LVDS,
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.name = "ch7017",
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.dvo_reg = DVOC,
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.dvo_srcdim_reg = DVOC_SRCDIM,
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.slave_addr = 0x75,
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.gpio = GMBUS_PIN_DPB,
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.dev_ops = &ch7017_ops,
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},
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{
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.type = INTEL_DVO_CHIP_TMDS,
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.name = "ns2501",
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.dvo_reg = DVOB,
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.dvo_srcdim_reg = DVOB_SRCDIM,
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.slave_addr = NS2501_ADDR,
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.dev_ops = &ns2501_ops,
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}
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};
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struct intel_dvo {
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struct intel_encoder base;
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struct intel_dvo_device dev;
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struct intel_connector *attached_connector;
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bool panel_wants_dither;
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};
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static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
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{
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return container_of(encoder, struct intel_dvo, base);
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}
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static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
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{
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return enc_to_dvo(intel_attached_encoder(connector));
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}
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static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
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{
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struct drm_device *dev = connector->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
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u32 tmp;
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tmp = I915_READ(intel_dvo->dev.dvo_reg);
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if (!(tmp & DVO_ENABLE))
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return false;
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return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
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}
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static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
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enum pipe *pipe)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
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u32 tmp;
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tmp = I915_READ(intel_dvo->dev.dvo_reg);
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if (!(tmp & DVO_ENABLE))
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return false;
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*pipe = PORT_TO_PIPE(tmp);
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return true;
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}
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static void intel_dvo_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
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u32 tmp, flags = 0;
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tmp = I915_READ(intel_dvo->dev.dvo_reg);
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if (tmp & DVO_HSYNC_ACTIVE_HIGH)
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flags |= DRM_MODE_FLAG_PHSYNC;
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else
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flags |= DRM_MODE_FLAG_NHSYNC;
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if (tmp & DVO_VSYNC_ACTIVE_HIGH)
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flags |= DRM_MODE_FLAG_PVSYNC;
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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pipe_config->base.adjusted_mode.flags |= flags;
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pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
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}
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static void intel_disable_dvo(struct intel_encoder *encoder,
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struct intel_crtc_state *old_crtc_state,
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struct drm_connector_state *old_conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
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i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
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u32 temp = I915_READ(dvo_reg);
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intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
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I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
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I915_READ(dvo_reg);
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}
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static void intel_enable_dvo(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
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i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
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u32 temp = I915_READ(dvo_reg);
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intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
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&pipe_config->base.mode,
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&pipe_config->base.adjusted_mode);
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I915_WRITE(dvo_reg, temp | DVO_ENABLE);
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I915_READ(dvo_reg);
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intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
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}
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static enum drm_mode_status
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intel_dvo_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
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const struct drm_display_mode *fixed_mode =
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to_intel_connector(connector)->panel.fixed_mode;
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int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
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int target_clock = mode->clock;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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return MODE_NO_DBLESCAN;
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/* XXX: Validate clock range */
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if (fixed_mode) {
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if (mode->hdisplay > fixed_mode->hdisplay)
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return MODE_PANEL;
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if (mode->vdisplay > fixed_mode->vdisplay)
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return MODE_PANEL;
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target_clock = fixed_mode->clock;
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}
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if (target_clock > max_dotclk)
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return MODE_CLOCK_HIGH;
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return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
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}
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static bool intel_dvo_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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{
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struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
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const struct drm_display_mode *fixed_mode =
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intel_dvo->attached_connector->panel.fixed_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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/* If we have timings from the BIOS for the panel, put them in
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* to the adjusted mode. The CRTC will be set up for this mode,
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* with the panel scaling set up to source from the H/VDisplay
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* of the original mode.
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*/
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if (fixed_mode)
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intel_fixed_panel_mode(fixed_mode, adjusted_mode);
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return true;
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}
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static void intel_dvo_pre_enable(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
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const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
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int pipe = crtc->pipe;
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u32 dvo_val;
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i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
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i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
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/* Save the data order, since I don't know what it should be set to. */
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dvo_val = I915_READ(dvo_reg) &
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(DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
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dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
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DVO_BLANK_ACTIVE_HIGH;
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if (pipe == 1)
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dvo_val |= DVO_PIPE_B_SELECT;
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dvo_val |= DVO_PIPE_STALL;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
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dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
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/*I915_WRITE(DVOB_SRCDIM,
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(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
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(adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
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I915_WRITE(dvo_srcdim_reg,
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(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
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(adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
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/*I915_WRITE(DVOB, dvo_val);*/
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I915_WRITE(dvo_reg, dvo_val);
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}
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/**
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* Detect the output connection on our DVO device.
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*
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* Unimplemented.
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*/
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static enum drm_connector_status
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intel_dvo_detect(struct drm_connector *connector, bool force)
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{
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struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
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DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
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connector->base.id, connector->name);
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return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
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}
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static int intel_dvo_get_modes(struct drm_connector *connector)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->dev);
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const struct drm_display_mode *fixed_mode =
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to_intel_connector(connector)->panel.fixed_mode;
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/* We should probably have an i2c driver get_modes function for those
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* devices which will have a fixed set of modes determined by the chip
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* (TV-out, for example), but for now with just TMDS and LVDS,
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* that's not the case.
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*/
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intel_ddc_get_modes(connector,
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intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
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if (!list_empty(&connector->probed_modes))
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|
return 1;
|
|
|
|
if (fixed_mode) {
|
|
struct drm_display_mode *mode;
|
|
mode = drm_mode_duplicate(connector->dev, fixed_mode);
|
|
if (mode) {
|
|
drm_mode_probed_add(connector, mode);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_dvo_destroy(struct drm_connector *connector)
|
|
{
|
|
drm_connector_cleanup(connector);
|
|
intel_panel_fini(&to_intel_connector(connector)->panel);
|
|
kfree(connector);
|
|
}
|
|
|
|
static const struct drm_connector_funcs intel_dvo_connector_funcs = {
|
|
.dpms = drm_atomic_helper_connector_dpms,
|
|
.detect = intel_dvo_detect,
|
|
.late_register = intel_connector_register,
|
|
.early_unregister = intel_connector_unregister,
|
|
.destroy = intel_dvo_destroy,
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
.atomic_get_property = intel_connector_atomic_get_property,
|
|
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
|
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
|
};
|
|
|
|
static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
|
|
.mode_valid = intel_dvo_mode_valid,
|
|
.get_modes = intel_dvo_get_modes,
|
|
};
|
|
|
|
static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
|
|
{
|
|
struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
|
|
|
|
if (intel_dvo->dev.dev_ops->destroy)
|
|
intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
|
|
|
|
intel_encoder_destroy(encoder);
|
|
}
|
|
|
|
static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
|
|
.destroy = intel_dvo_enc_destroy,
|
|
};
|
|
|
|
/**
|
|
* Attempts to get a fixed panel timing for LVDS (currently only the i830).
|
|
*
|
|
* Other chips with DVO LVDS will need to extend this to deal with the LVDS
|
|
* chip being on DVOB/C and having multiple pipes.
|
|
*/
|
|
static struct drm_display_mode *
|
|
intel_dvo_get_current_mode(struct drm_connector *connector)
|
|
{
|
|
struct drm_device *dev = connector->dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
|
|
uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
|
|
struct drm_display_mode *mode = NULL;
|
|
|
|
/* If the DVO port is active, that'll be the LVDS, so we can pull out
|
|
* its timings to get how the BIOS set up the panel.
|
|
*/
|
|
if (dvo_val & DVO_ENABLE) {
|
|
struct drm_crtc *crtc;
|
|
int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;
|
|
|
|
crtc = intel_get_crtc_for_pipe(dev, pipe);
|
|
if (crtc) {
|
|
mode = intel_crtc_mode_get(dev, crtc);
|
|
if (mode) {
|
|
mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
|
|
mode->flags |= DRM_MODE_FLAG_PHSYNC;
|
|
if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
|
|
mode->flags |= DRM_MODE_FLAG_PVSYNC;
|
|
}
|
|
}
|
|
}
|
|
|
|
return mode;
|
|
}
|
|
|
|
static char intel_dvo_port_name(i915_reg_t dvo_reg)
|
|
{
|
|
if (i915_mmio_reg_equal(dvo_reg, DVOA))
|
|
return 'A';
|
|
else if (i915_mmio_reg_equal(dvo_reg, DVOB))
|
|
return 'B';
|
|
else if (i915_mmio_reg_equal(dvo_reg, DVOC))
|
|
return 'C';
|
|
else
|
|
return '?';
|
|
}
|
|
|
|
void intel_dvo_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct intel_encoder *intel_encoder;
|
|
struct intel_dvo *intel_dvo;
|
|
struct intel_connector *intel_connector;
|
|
int i;
|
|
int encoder_type = DRM_MODE_ENCODER_NONE;
|
|
|
|
intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
|
|
if (!intel_dvo)
|
|
return;
|
|
|
|
intel_connector = intel_connector_alloc();
|
|
if (!intel_connector) {
|
|
kfree(intel_dvo);
|
|
return;
|
|
}
|
|
|
|
intel_dvo->attached_connector = intel_connector;
|
|
|
|
intel_encoder = &intel_dvo->base;
|
|
|
|
intel_encoder->disable = intel_disable_dvo;
|
|
intel_encoder->enable = intel_enable_dvo;
|
|
intel_encoder->get_hw_state = intel_dvo_get_hw_state;
|
|
intel_encoder->get_config = intel_dvo_get_config;
|
|
intel_encoder->compute_config = intel_dvo_compute_config;
|
|
intel_encoder->pre_enable = intel_dvo_pre_enable;
|
|
intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
|
|
|
|
/* Now, try to find a controller */
|
|
for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
|
|
struct i2c_adapter *i2c;
|
|
int gpio;
|
|
bool dvoinit;
|
|
enum pipe pipe;
|
|
uint32_t dpll[I915_MAX_PIPES];
|
|
|
|
/* Allow the I2C driver info to specify the GPIO to be used in
|
|
* special cases, but otherwise default to what's defined
|
|
* in the spec.
|
|
*/
|
|
if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
|
|
gpio = dvo->gpio;
|
|
else if (dvo->type == INTEL_DVO_CHIP_LVDS)
|
|
gpio = GMBUS_PIN_SSC;
|
|
else
|
|
gpio = GMBUS_PIN_DPB;
|
|
|
|
/* Set up the I2C bus necessary for the chip we're probing.
|
|
* It appears that everything is on GPIOE except for panels
|
|
* on i830 laptops, which are on GPIOB (DVOA).
|
|
*/
|
|
i2c = intel_gmbus_get_adapter(dev_priv, gpio);
|
|
|
|
intel_dvo->dev = *dvo;
|
|
|
|
/* GMBUS NAK handling seems to be unstable, hence let the
|
|
* transmitter detection run in bit banging mode for now.
|
|
*/
|
|
intel_gmbus_force_bit(i2c, true);
|
|
|
|
/* ns2501 requires the DVO 2x clock before it will
|
|
* respond to i2c accesses, so make sure we have
|
|
* have the clock enabled before we attempt to
|
|
* initialize the device.
|
|
*/
|
|
for_each_pipe(dev_priv, pipe) {
|
|
dpll[pipe] = I915_READ(DPLL(pipe));
|
|
I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
|
|
}
|
|
|
|
dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
|
|
|
|
/* restore the DVO 2x clock state to original */
|
|
for_each_pipe(dev_priv, pipe) {
|
|
I915_WRITE(DPLL(pipe), dpll[pipe]);
|
|
}
|
|
|
|
intel_gmbus_force_bit(i2c, false);
|
|
|
|
if (!dvoinit)
|
|
continue;
|
|
|
|
drm_encoder_init(dev, &intel_encoder->base,
|
|
&intel_dvo_enc_funcs, encoder_type,
|
|
"DVO %c", intel_dvo_port_name(dvo->dvo_reg));
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_DVO;
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
|
|
switch (dvo->type) {
|
|
case INTEL_DVO_CHIP_TMDS:
|
|
intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
|
|
(1 << INTEL_OUTPUT_DVO);
|
|
drm_connector_init(dev, connector,
|
|
&intel_dvo_connector_funcs,
|
|
DRM_MODE_CONNECTOR_DVII);
|
|
encoder_type = DRM_MODE_ENCODER_TMDS;
|
|
break;
|
|
case INTEL_DVO_CHIP_LVDS:
|
|
intel_encoder->cloneable = 0;
|
|
drm_connector_init(dev, connector,
|
|
&intel_dvo_connector_funcs,
|
|
DRM_MODE_CONNECTOR_LVDS);
|
|
encoder_type = DRM_MODE_ENCODER_LVDS;
|
|
break;
|
|
}
|
|
|
|
drm_connector_helper_add(connector,
|
|
&intel_dvo_connector_helper_funcs);
|
|
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
|
connector->interlace_allowed = false;
|
|
connector->doublescan_allowed = false;
|
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
if (dvo->type == INTEL_DVO_CHIP_LVDS) {
|
|
/* For our LVDS chipsets, we should hopefully be able
|
|
* to dig the fixed panel mode out of the BIOS data.
|
|
* However, it's in a different format from the BIOS
|
|
* data on chipsets with integrated LVDS (stored in AIM
|
|
* headers, likely), so for now, just get the current
|
|
* mode being output through DVO.
|
|
*/
|
|
intel_panel_init(&intel_connector->panel,
|
|
intel_dvo_get_current_mode(connector),
|
|
NULL);
|
|
intel_dvo->panel_wants_dither = true;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
kfree(intel_dvo);
|
|
kfree(intel_connector);
|
|
}
|