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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this file is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this file is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190523091650.284757242@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
219 lines
5 KiB
C
219 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2015, Daniel Thompson
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/hw_random.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#define RNG_CR 0x00
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#define RNG_CR_RNGEN BIT(2)
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#define RNG_CR_CED BIT(5)
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#define RNG_SR 0x04
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#define RNG_SR_SEIS BIT(6)
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#define RNG_SR_CEIS BIT(5)
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#define RNG_SR_DRDY BIT(0)
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#define RNG_DR 0x08
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struct stm32_rng_private {
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struct hwrng rng;
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void __iomem *base;
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struct clk *clk;
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struct reset_control *rst;
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bool ced;
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};
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static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
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{
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struct stm32_rng_private *priv =
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container_of(rng, struct stm32_rng_private, rng);
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u32 sr;
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int retval = 0;
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pm_runtime_get_sync((struct device *) priv->rng.priv);
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while (max > sizeof(u32)) {
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sr = readl_relaxed(priv->base + RNG_SR);
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/* Manage timeout which is based on timer and take */
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/* care of initial delay time when enabling rng */
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if (!sr && wait) {
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retval = readl_relaxed_poll_timeout_atomic(priv->base
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+ RNG_SR,
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sr, sr,
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10, 50000);
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if (retval)
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dev_err((struct device *)priv->rng.priv,
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"%s: timeout %x!\n", __func__, sr);
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}
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/* If error detected or data not ready... */
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if (sr != RNG_SR_DRDY) {
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if (WARN_ONCE(sr & (RNG_SR_SEIS | RNG_SR_CEIS),
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"bad RNG status - %x\n", sr))
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writel_relaxed(0, priv->base + RNG_SR);
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break;
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}
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*(u32 *)data = readl_relaxed(priv->base + RNG_DR);
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retval += sizeof(u32);
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data += sizeof(u32);
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max -= sizeof(u32);
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}
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pm_runtime_mark_last_busy((struct device *) priv->rng.priv);
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pm_runtime_put_sync_autosuspend((struct device *) priv->rng.priv);
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return retval || !wait ? retval : -EIO;
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}
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static int stm32_rng_init(struct hwrng *rng)
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{
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struct stm32_rng_private *priv =
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container_of(rng, struct stm32_rng_private, rng);
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int err;
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err = clk_prepare_enable(priv->clk);
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if (err)
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return err;
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if (priv->ced)
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writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
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else
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writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
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priv->base + RNG_CR);
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/* clear error indicators */
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writel_relaxed(0, priv->base + RNG_SR);
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return 0;
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}
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static void stm32_rng_cleanup(struct hwrng *rng)
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{
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struct stm32_rng_private *priv =
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container_of(rng, struct stm32_rng_private, rng);
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writel_relaxed(0, priv->base + RNG_CR);
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clk_disable_unprepare(priv->clk);
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}
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static int stm32_rng_probe(struct platform_device *ofdev)
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{
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struct device *dev = &ofdev->dev;
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struct device_node *np = ofdev->dev.of_node;
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struct stm32_rng_private *priv;
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struct resource res;
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int err;
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priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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err = of_address_to_resource(np, 0, &res);
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if (err)
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return err;
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priv->base = devm_ioremap_resource(dev, &res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->clk = devm_clk_get(&ofdev->dev, NULL);
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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priv->rst = devm_reset_control_get(&ofdev->dev, NULL);
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if (!IS_ERR(priv->rst)) {
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reset_control_assert(priv->rst);
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udelay(2);
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reset_control_deassert(priv->rst);
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}
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priv->ced = of_property_read_bool(np, "clock-error-detect");
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dev_set_drvdata(dev, priv);
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priv->rng.name = dev_driver_string(dev),
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#ifndef CONFIG_PM
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priv->rng.init = stm32_rng_init,
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priv->rng.cleanup = stm32_rng_cleanup,
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#endif
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priv->rng.read = stm32_rng_read,
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priv->rng.priv = (unsigned long) dev;
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priv->rng.quality = 900;
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pm_runtime_set_autosuspend_delay(dev, 100);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_enable(dev);
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return devm_hwrng_register(dev, &priv->rng);
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}
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static int stm32_rng_remove(struct platform_device *ofdev)
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{
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pm_runtime_disable(&ofdev->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int stm32_rng_runtime_suspend(struct device *dev)
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{
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struct stm32_rng_private *priv = dev_get_drvdata(dev);
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stm32_rng_cleanup(&priv->rng);
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return 0;
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}
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static int stm32_rng_runtime_resume(struct device *dev)
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{
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struct stm32_rng_private *priv = dev_get_drvdata(dev);
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return stm32_rng_init(&priv->rng);
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}
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#endif
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static const struct dev_pm_ops stm32_rng_pm_ops = {
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SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
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stm32_rng_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct of_device_id stm32_rng_match[] = {
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{
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.compatible = "st,stm32-rng",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_rng_match);
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static struct platform_driver stm32_rng_driver = {
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.driver = {
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.name = "stm32-rng",
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.pm = &stm32_rng_pm_ops,
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.of_match_table = stm32_rng_match,
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},
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.probe = stm32_rng_probe,
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.remove = stm32_rng_remove,
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};
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module_platform_driver(stm32_rng_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Daniel Thompson <daniel.thompson@linaro.org>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 RNG device driver");
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