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Marc Zyngier bb0fed1c60 irqchip/sifive-plic: Switch to fasteoi flow
The SiFive PLIC interrupt controller seems to have all the HW
features to support the fasteoi flow, but the driver seems to be
stuck in a distant past. Bring it into the 21st century.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Palmer Dabbelt <palmer@sifive.com> (QEMU Boot)
Tested-by: Darius Rad <darius@bluespec.com> (on 2 HW PLIC implementations)
Tested-by: Paul Walmsley <paul.walmsley@sifive.com> (HiFive Unleashed)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/8636gxskmj.wl-maz@kernel.org
2019-09-18 12:29:52 +01:00
arch irqchip/mmp: Mask off interrupts from other cores 2019-08-30 15:23:30 +01:00
block
certs
crypto
Documentation irqchip/atmel-aic5: Add support for sam9x60 irqchip 2019-09-09 18:11:51 +01:00
drivers irqchip/sifive-plic: Switch to fasteoi flow 2019-09-18 12:29:52 +01:00
fs
include irqchip: Add include guard to irq-partition-percpu.h 2019-08-20 10:35:46 +01:00
init
ipc
kernel irqdomain: Add the missing assignment of domain->fwnode for named fwnode 2019-09-03 09:16:50 +01:00
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Linux kernel
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