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dc8ea9204b
There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
17 lines
495 B
Text
17 lines
495 B
Text
* Marvell Tauros2 Cache
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Required properties:
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- compatible : Should be "marvell,tauros2-cache".
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- marvell,tauros2-cache-features : Specify the features supported for the
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tauros2 cache.
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The features including
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CACHE_TAUROS2_PREFETCH_ON (1 << 0)
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CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
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The definition can be found at
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arch/arm/include/asm/hardware/cache-tauros2.h
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Example:
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L2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0x3>;
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};
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