96 lines
2.5 KiB
YAML
96 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display split
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display split, namely SPLIT, is used to split stream to two
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encoders.
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SPLIT device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt8173-disp-split
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- mediatek,mt8195-mdp3-split
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- items:
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- const: mediatek,mt6795-disp-split
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- const: mediatek,mt8173-disp-split
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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mediatek,gce-client-reg:
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description:
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The register of display function block to be set by gce. There are 4 arguments,
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such as gce node, subsys id, offset and register size. The subsys id that is
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mapping to the register of display function blocks is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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maxItems: 1
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clocks:
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items:
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- description: SPLIT Clock
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required:
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- compatible
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- reg
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- power-domains
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- clocks
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt8195-mdp3-split
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then:
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required:
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- mediatek,gce-client-reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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split0: split@14018000 {
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compatible = "mediatek,mt8173-disp-split";
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reg = <0 0x14018000 0 0x1000>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
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};
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};
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