80 lines
1.8 KiB
YAML
80 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2M Clocked Serial Interface (CSI)
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maintainers:
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- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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const: renesas,rzv2m-csi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: The clock used to generate the output clock (CSICLK)
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- description: Internal clock to access the registers (PCLK)
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clock-names:
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items:
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- const: csiclk
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- const: pclk
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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renesas,csi-no-ss:
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type: boolean
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description:
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The CSI Slave Selection (SS) pin won't be used to enable transmission and
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reception. Only available when in target mode.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- power-domains
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- '#address-cells'
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- '#size-cells'
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dependencies:
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renesas,csi-no-ss: [ spi-slave ]
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a09g011-cpg.h>
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csi4: spi@a4020200 {
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compatible = "renesas,rzv2m-csi";
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reg = <0xa4020200 0x80>;
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interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
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<&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
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clock-names = "csiclk", "pclk";
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resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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