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![Charles Keepax](/assets/img/avatar_default.png)
Some error paths in regmap_irq_thread put the pm_runtime others do not, there is no reason to leave the pm_runtime enabled in some cases so update those paths to also put the pm_runtime. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20190812092409.21593-1-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
992 lines
25 KiB
C
992 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// regmap based irq_chip
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//
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// Copyright 2011 Wolfson Microelectronics plc
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//
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// Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "internal.h"
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struct regmap_irq_chip_data {
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struct mutex lock;
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struct irq_chip irq_chip;
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struct regmap *map;
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const struct regmap_irq_chip *chip;
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int irq_base;
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struct irq_domain *domain;
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int irq;
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int wake_count;
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void *status_reg_buf;
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unsigned int *main_status_buf;
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unsigned int *status_buf;
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unsigned int *mask_buf;
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unsigned int *mask_buf_def;
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unsigned int *wake_buf;
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unsigned int *type_buf;
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unsigned int *type_buf_def;
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unsigned int irq_reg_stride;
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unsigned int type_reg_stride;
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bool clear_status:1;
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};
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static inline const
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struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
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int irq)
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{
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return &data->chip->irqs[irq];
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}
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static void regmap_irq_lock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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mutex_lock(&d->lock);
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}
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static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
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unsigned int reg, unsigned int mask,
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unsigned int val)
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{
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if (d->chip->mask_writeonly)
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return regmap_write_bits(d->map, reg, mask, val);
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else
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return regmap_update_bits(d->map, reg, mask, val);
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}
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static void regmap_irq_sync_unlock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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int i, ret;
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u32 reg;
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u32 unmask_offset;
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u32 val;
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if (d->chip->runtime_pm) {
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ret = pm_runtime_get_sync(map->dev);
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if (ret < 0)
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dev_err(map->dev, "IRQ sync failed to resume: %d\n",
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ret);
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}
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if (d->clear_status) {
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for (i = 0; i < d->chip->num_regs; i++) {
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reg = d->chip->status_base +
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(i * map->reg_stride * d->irq_reg_stride);
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ret = regmap_read(map, reg, &val);
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if (ret)
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dev_err(d->map->dev,
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"Failed to clear the interrupt status bits\n");
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}
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d->clear_status = false;
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}
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/*
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* If there's been a change in the mask write it back to the
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* hardware. We rely on the use of the regmap core cache to
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* suppress pointless writes.
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*/
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for (i = 0; i < d->chip->num_regs; i++) {
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if (!d->chip->mask_base)
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continue;
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reg = d->chip->mask_base +
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(i * map->reg_stride * d->irq_reg_stride);
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if (d->chip->mask_invert) {
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ret = regmap_irq_update_bits(d, reg,
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d->mask_buf_def[i], ~d->mask_buf[i]);
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} else if (d->chip->unmask_base) {
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/* set mask with mask_base register */
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ret = regmap_irq_update_bits(d, reg,
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d->mask_buf_def[i], ~d->mask_buf[i]);
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if (ret < 0)
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dev_err(d->map->dev,
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"Failed to sync unmasks in %x\n",
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reg);
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unmask_offset = d->chip->unmask_base -
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d->chip->mask_base;
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/* clear mask with unmask_base register */
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ret = regmap_irq_update_bits(d,
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reg + unmask_offset,
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d->mask_buf_def[i],
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d->mask_buf[i]);
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} else {
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ret = regmap_irq_update_bits(d, reg,
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d->mask_buf_def[i], d->mask_buf[i]);
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}
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if (ret != 0)
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dev_err(d->map->dev, "Failed to sync masks in %x\n",
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reg);
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reg = d->chip->wake_base +
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(i * map->reg_stride * d->irq_reg_stride);
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if (d->wake_buf) {
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if (d->chip->wake_invert)
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ret = regmap_irq_update_bits(d, reg,
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d->mask_buf_def[i],
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~d->wake_buf[i]);
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else
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ret = regmap_irq_update_bits(d, reg,
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d->mask_buf_def[i],
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d->wake_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev,
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"Failed to sync wakes in %x: %d\n",
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reg, ret);
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}
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if (!d->chip->init_ack_masked)
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continue;
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/*
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* Ack all the masked interrupts unconditionally,
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* OR if there is masked interrupt which hasn't been Acked,
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* it'll be ignored in irq handler, then may introduce irq storm
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*/
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if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
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reg = d->chip->ack_base +
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(i * map->reg_stride * d->irq_reg_stride);
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/* some chips ack by write 0 */
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if (d->chip->ack_invert)
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ret = regmap_write(map, reg, ~d->mask_buf[i]);
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else
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ret = regmap_write(map, reg, d->mask_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
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reg, ret);
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}
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}
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/* Don't update the type bits if we're using mask bits for irq type. */
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if (!d->chip->type_in_mask) {
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for (i = 0; i < d->chip->num_type_reg; i++) {
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if (!d->type_buf_def[i])
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continue;
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reg = d->chip->type_base +
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(i * map->reg_stride * d->type_reg_stride);
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if (d->chip->type_invert)
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ret = regmap_irq_update_bits(d, reg,
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d->type_buf_def[i], ~d->type_buf[i]);
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else
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ret = regmap_irq_update_bits(d, reg,
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d->type_buf_def[i], d->type_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev, "Failed to sync type in %x\n",
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reg);
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}
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}
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if (d->chip->runtime_pm)
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pm_runtime_put(map->dev);
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/* If we've changed our wakeup count propagate it to the parent */
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if (d->wake_count < 0)
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for (i = d->wake_count; i < 0; i++)
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irq_set_irq_wake(d->irq, 0);
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else if (d->wake_count > 0)
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for (i = 0; i < d->wake_count; i++)
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irq_set_irq_wake(d->irq, 1);
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d->wake_count = 0;
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mutex_unlock(&d->lock);
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}
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static void regmap_irq_enable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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unsigned int mask, type;
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type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
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/*
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* The type_in_mask flag means that the underlying hardware uses
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* separate mask bits for rising and falling edge interrupts, but
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* we want to make them into a single virtual interrupt with
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* configurable edge.
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*
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* If the interrupt we're enabling defines the falling or rising
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* masks then instead of using the regular mask bits for this
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* interrupt, use the value previously written to the type buffer
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* at the corresponding offset in regmap_irq_set_type().
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*/
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if (d->chip->type_in_mask && type)
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mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
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else
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mask = irq_data->mask;
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if (d->chip->clear_on_unmask)
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d->clear_status = true;
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d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
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}
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static void regmap_irq_disable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
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}
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static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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int reg;
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const struct regmap_irq_type *t = &irq_data->type;
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if ((t->types_supported & type) != type)
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return 0;
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reg = t->type_reg_offset / map->reg_stride;
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if (t->type_reg_mask)
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d->type_buf[reg] &= ~t->type_reg_mask;
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else
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d->type_buf[reg] &= ~(t->type_falling_val |
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t->type_rising_val |
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t->type_level_low_val |
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t->type_level_high_val);
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switch (type) {
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case IRQ_TYPE_EDGE_FALLING:
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d->type_buf[reg] |= t->type_falling_val;
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break;
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case IRQ_TYPE_EDGE_RISING:
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d->type_buf[reg] |= t->type_rising_val;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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d->type_buf[reg] |= (t->type_falling_val |
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t->type_rising_val);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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d->type_buf[reg] |= t->type_level_high_val;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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d->type_buf[reg] |= t->type_level_low_val;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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if (on) {
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if (d->wake_buf)
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d->wake_buf[irq_data->reg_offset / map->reg_stride]
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&= ~irq_data->mask;
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d->wake_count++;
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} else {
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if (d->wake_buf)
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d->wake_buf[irq_data->reg_offset / map->reg_stride]
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|= irq_data->mask;
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d->wake_count--;
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}
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return 0;
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}
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static const struct irq_chip regmap_irq_chip = {
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.irq_bus_lock = regmap_irq_lock,
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.irq_bus_sync_unlock = regmap_irq_sync_unlock,
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.irq_disable = regmap_irq_disable,
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.irq_enable = regmap_irq_enable,
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.irq_set_type = regmap_irq_set_type,
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.irq_set_wake = regmap_irq_set_wake,
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};
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static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
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unsigned int b)
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{
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const struct regmap_irq_chip *chip = data->chip;
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struct regmap *map = data->map;
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struct regmap_irq_sub_irq_map *subreg;
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int i, ret = 0;
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if (!chip->sub_reg_offsets) {
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/* Assume linear mapping */
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ret = regmap_read(map, chip->status_base +
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(b * map->reg_stride * data->irq_reg_stride),
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&data->status_buf[b]);
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} else {
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subreg = &chip->sub_reg_offsets[b];
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for (i = 0; i < subreg->num_regs; i++) {
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unsigned int offset = subreg->offset[i];
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ret = regmap_read(map, chip->status_base + offset,
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&data->status_buf[offset]);
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if (ret)
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break;
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}
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}
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return ret;
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}
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static irqreturn_t regmap_irq_thread(int irq, void *d)
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{
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struct regmap_irq_chip_data *data = d;
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const struct regmap_irq_chip *chip = data->chip;
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struct regmap *map = data->map;
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int ret, i;
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bool handled = false;
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u32 reg;
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if (chip->handle_pre_irq)
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chip->handle_pre_irq(chip->irq_drv_data);
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if (chip->runtime_pm) {
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ret = pm_runtime_get_sync(map->dev);
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if (ret < 0) {
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dev_err(map->dev, "IRQ thread failed to resume: %d\n",
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ret);
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goto exit;
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}
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}
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/*
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* Read only registers with active IRQs if the chip has 'main status
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* register'. Else read in the statuses, using a single bulk read if
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* possible in order to reduce the I/O overheads.
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*/
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if (chip->num_main_regs) {
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unsigned int max_main_bits;
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unsigned long size;
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size = chip->num_regs * sizeof(unsigned int);
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max_main_bits = (chip->num_main_status_bits) ?
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chip->num_main_status_bits : chip->num_regs;
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/* Clear the status buf as we don't read all status regs */
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memset(data->status_buf, 0, size);
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/* We could support bulk read for main status registers
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* but I don't expect to see devices with really many main
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* status registers so let's only support single reads for the
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* sake of simplicity. and add bulk reads only if needed
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*/
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for (i = 0; i < chip->num_main_regs; i++) {
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ret = regmap_read(map, chip->main_status +
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(i * map->reg_stride
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* data->irq_reg_stride),
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&data->main_status_buf[i]);
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if (ret) {
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dev_err(map->dev,
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"Failed to read IRQ status %d\n",
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ret);
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goto exit;
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}
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}
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/* Read sub registers with active IRQs */
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for (i = 0; i < chip->num_main_regs; i++) {
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unsigned int b;
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const unsigned long mreg = data->main_status_buf[i];
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for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
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if (i * map->format.val_bytes * 8 + b >
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max_main_bits)
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break;
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ret = read_sub_irq_data(data, b);
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if (ret != 0) {
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dev_err(map->dev,
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"Failed to read IRQ status %d\n",
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ret);
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goto exit;
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}
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}
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}
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} else if (!map->use_single_read && map->reg_stride == 1 &&
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data->irq_reg_stride == 1) {
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u8 *buf8 = data->status_reg_buf;
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u16 *buf16 = data->status_reg_buf;
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u32 *buf32 = data->status_reg_buf;
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BUG_ON(!data->status_reg_buf);
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ret = regmap_bulk_read(map, chip->status_base,
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data->status_reg_buf,
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chip->num_regs);
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if (ret != 0) {
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dev_err(map->dev, "Failed to read IRQ status: %d\n",
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ret);
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goto exit;
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}
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for (i = 0; i < data->chip->num_regs; i++) {
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switch (map->format.val_bytes) {
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case 1:
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data->status_buf[i] = buf8[i];
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break;
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case 2:
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data->status_buf[i] = buf16[i];
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break;
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case 4:
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data->status_buf[i] = buf32[i];
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break;
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default:
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BUG();
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goto exit;
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}
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}
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} else {
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for (i = 0; i < data->chip->num_regs; i++) {
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ret = regmap_read(map, chip->status_base +
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(i * map->reg_stride
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* data->irq_reg_stride),
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&data->status_buf[i]);
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if (ret != 0) {
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dev_err(map->dev,
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"Failed to read IRQ status: %d\n",
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ret);
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goto exit;
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}
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}
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}
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/*
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* Ignore masked IRQs and ack if we need to; we ack early so
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* there is no race between handling and acknowleding the
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* interrupt. We assume that typically few of the interrupts
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* will fire simultaneously so don't worry about overhead from
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* doing a write per register.
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*/
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for (i = 0; i < data->chip->num_regs; i++) {
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data->status_buf[i] &= ~data->mask_buf[i];
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|
|
if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
|
|
reg = chip->ack_base +
|
|
(i * map->reg_stride * data->irq_reg_stride);
|
|
ret = regmap_write(map, reg, data->status_buf[i]);
|
|
if (ret != 0)
|
|
dev_err(map->dev, "Failed to ack 0x%x: %d\n",
|
|
reg, ret);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < chip->num_irqs; i++) {
|
|
if (data->status_buf[chip->irqs[i].reg_offset /
|
|
map->reg_stride] & chip->irqs[i].mask) {
|
|
handle_nested_irq(irq_find_mapping(data->domain, i));
|
|
handled = true;
|
|
}
|
|
}
|
|
|
|
exit:
|
|
if (chip->runtime_pm)
|
|
pm_runtime_put(map->dev);
|
|
|
|
if (chip->handle_post_irq)
|
|
chip->handle_post_irq(chip->irq_drv_data);
|
|
|
|
if (handled)
|
|
return IRQ_HANDLED;
|
|
else
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
struct regmap_irq_chip_data *data = h->host_data;
|
|
|
|
irq_set_chip_data(virq, data);
|
|
irq_set_chip(virq, &data->irq_chip);
|
|
irq_set_nested_thread(virq, 1);
|
|
irq_set_parent(virq, data->irq);
|
|
irq_set_noprobe(virq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops regmap_domain_ops = {
|
|
.map = regmap_irq_map,
|
|
.xlate = irq_domain_xlate_onetwocell,
|
|
};
|
|
|
|
/**
|
|
* regmap_add_irq_chip() - Use standard regmap IRQ controller handling
|
|
*
|
|
* @map: The regmap for the device.
|
|
* @irq: The IRQ the device uses to signal interrupts.
|
|
* @irq_flags: The IRQF_ flags to use for the primary interrupt.
|
|
* @irq_base: Allocate at specific IRQ number if irq_base > 0.
|
|
* @chip: Configuration for the interrupt controller.
|
|
* @data: Runtime data structure for the controller, allocated on success.
|
|
*
|
|
* Returns 0 on success or an errno on failure.
|
|
*
|
|
* In order for this to be efficient the chip really should use a
|
|
* register cache. The chip driver is responsible for restoring the
|
|
* register values used by the IRQ controller over suspend and resume.
|
|
*/
|
|
int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
|
|
int irq_base, const struct regmap_irq_chip *chip,
|
|
struct regmap_irq_chip_data **data)
|
|
{
|
|
struct regmap_irq_chip_data *d;
|
|
int i;
|
|
int ret = -ENOMEM;
|
|
int num_type_reg;
|
|
u32 reg;
|
|
u32 unmask_offset;
|
|
|
|
if (chip->num_regs <= 0)
|
|
return -EINVAL;
|
|
|
|
if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < chip->num_irqs; i++) {
|
|
if (chip->irqs[i].reg_offset % map->reg_stride)
|
|
return -EINVAL;
|
|
if (chip->irqs[i].reg_offset / map->reg_stride >=
|
|
chip->num_regs)
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (irq_base) {
|
|
irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
|
|
if (irq_base < 0) {
|
|
dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
|
|
irq_base);
|
|
return irq_base;
|
|
}
|
|
}
|
|
|
|
d = kzalloc(sizeof(*d), GFP_KERNEL);
|
|
if (!d)
|
|
return -ENOMEM;
|
|
|
|
if (chip->num_main_regs) {
|
|
d->main_status_buf = kcalloc(chip->num_main_regs,
|
|
sizeof(unsigned int),
|
|
GFP_KERNEL);
|
|
|
|
if (!d->main_status_buf)
|
|
goto err_alloc;
|
|
}
|
|
|
|
d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
|
|
GFP_KERNEL);
|
|
if (!d->status_buf)
|
|
goto err_alloc;
|
|
|
|
d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
|
|
GFP_KERNEL);
|
|
if (!d->mask_buf)
|
|
goto err_alloc;
|
|
|
|
d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
|
|
GFP_KERNEL);
|
|
if (!d->mask_buf_def)
|
|
goto err_alloc;
|
|
|
|
if (chip->wake_base) {
|
|
d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
|
|
GFP_KERNEL);
|
|
if (!d->wake_buf)
|
|
goto err_alloc;
|
|
}
|
|
|
|
num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
|
|
if (num_type_reg) {
|
|
d->type_buf_def = kcalloc(num_type_reg,
|
|
sizeof(unsigned int), GFP_KERNEL);
|
|
if (!d->type_buf_def)
|
|
goto err_alloc;
|
|
|
|
d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
|
|
GFP_KERNEL);
|
|
if (!d->type_buf)
|
|
goto err_alloc;
|
|
}
|
|
|
|
d->irq_chip = regmap_irq_chip;
|
|
d->irq_chip.name = chip->name;
|
|
d->irq = irq;
|
|
d->map = map;
|
|
d->chip = chip;
|
|
d->irq_base = irq_base;
|
|
|
|
if (chip->irq_reg_stride)
|
|
d->irq_reg_stride = chip->irq_reg_stride;
|
|
else
|
|
d->irq_reg_stride = 1;
|
|
|
|
if (chip->type_reg_stride)
|
|
d->type_reg_stride = chip->type_reg_stride;
|
|
else
|
|
d->type_reg_stride = 1;
|
|
|
|
if (!map->use_single_read && map->reg_stride == 1 &&
|
|
d->irq_reg_stride == 1) {
|
|
d->status_reg_buf = kmalloc_array(chip->num_regs,
|
|
map->format.val_bytes,
|
|
GFP_KERNEL);
|
|
if (!d->status_reg_buf)
|
|
goto err_alloc;
|
|
}
|
|
|
|
mutex_init(&d->lock);
|
|
|
|
for (i = 0; i < chip->num_irqs; i++)
|
|
d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
|
|
|= chip->irqs[i].mask;
|
|
|
|
/* Mask all the interrupts by default */
|
|
for (i = 0; i < chip->num_regs; i++) {
|
|
d->mask_buf[i] = d->mask_buf_def[i];
|
|
if (!chip->mask_base)
|
|
continue;
|
|
|
|
reg = chip->mask_base +
|
|
(i * map->reg_stride * d->irq_reg_stride);
|
|
if (chip->mask_invert)
|
|
ret = regmap_irq_update_bits(d, reg,
|
|
d->mask_buf[i], ~d->mask_buf[i]);
|
|
else if (d->chip->unmask_base) {
|
|
unmask_offset = d->chip->unmask_base -
|
|
d->chip->mask_base;
|
|
ret = regmap_irq_update_bits(d,
|
|
reg + unmask_offset,
|
|
d->mask_buf[i],
|
|
d->mask_buf[i]);
|
|
} else
|
|
ret = regmap_irq_update_bits(d, reg,
|
|
d->mask_buf[i], d->mask_buf[i]);
|
|
if (ret != 0) {
|
|
dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
|
|
reg, ret);
|
|
goto err_alloc;
|
|
}
|
|
|
|
if (!chip->init_ack_masked)
|
|
continue;
|
|
|
|
/* Ack masked but set interrupts */
|
|
reg = chip->status_base +
|
|
(i * map->reg_stride * d->irq_reg_stride);
|
|
ret = regmap_read(map, reg, &d->status_buf[i]);
|
|
if (ret != 0) {
|
|
dev_err(map->dev, "Failed to read IRQ status: %d\n",
|
|
ret);
|
|
goto err_alloc;
|
|
}
|
|
|
|
if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
|
|
reg = chip->ack_base +
|
|
(i * map->reg_stride * d->irq_reg_stride);
|
|
if (chip->ack_invert)
|
|
ret = regmap_write(map, reg,
|
|
~(d->status_buf[i] & d->mask_buf[i]));
|
|
else
|
|
ret = regmap_write(map, reg,
|
|
d->status_buf[i] & d->mask_buf[i]);
|
|
if (ret != 0) {
|
|
dev_err(map->dev, "Failed to ack 0x%x: %d\n",
|
|
reg, ret);
|
|
goto err_alloc;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Wake is disabled by default */
|
|
if (d->wake_buf) {
|
|
for (i = 0; i < chip->num_regs; i++) {
|
|
d->wake_buf[i] = d->mask_buf_def[i];
|
|
reg = chip->wake_base +
|
|
(i * map->reg_stride * d->irq_reg_stride);
|
|
|
|
if (chip->wake_invert)
|
|
ret = regmap_irq_update_bits(d, reg,
|
|
d->mask_buf_def[i],
|
|
0);
|
|
else
|
|
ret = regmap_irq_update_bits(d, reg,
|
|
d->mask_buf_def[i],
|
|
d->wake_buf[i]);
|
|
if (ret != 0) {
|
|
dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
|
|
reg, ret);
|
|
goto err_alloc;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (chip->num_type_reg && !chip->type_in_mask) {
|
|
for (i = 0; i < chip->num_type_reg; ++i) {
|
|
reg = chip->type_base +
|
|
(i * map->reg_stride * d->type_reg_stride);
|
|
|
|
ret = regmap_read(map, reg, &d->type_buf_def[i]);
|
|
|
|
if (d->chip->type_invert)
|
|
d->type_buf_def[i] = ~d->type_buf_def[i];
|
|
|
|
if (ret) {
|
|
dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
|
|
reg, ret);
|
|
goto err_alloc;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (irq_base)
|
|
d->domain = irq_domain_add_legacy(map->dev->of_node,
|
|
chip->num_irqs, irq_base, 0,
|
|
®map_domain_ops, d);
|
|
else
|
|
d->domain = irq_domain_add_linear(map->dev->of_node,
|
|
chip->num_irqs,
|
|
®map_domain_ops, d);
|
|
if (!d->domain) {
|
|
dev_err(map->dev, "Failed to create IRQ domain\n");
|
|
ret = -ENOMEM;
|
|
goto err_alloc;
|
|
}
|
|
|
|
ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
|
|
irq_flags | IRQF_ONESHOT,
|
|
chip->name, d);
|
|
if (ret != 0) {
|
|
dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
|
|
irq, chip->name, ret);
|
|
goto err_domain;
|
|
}
|
|
|
|
*data = d;
|
|
|
|
return 0;
|
|
|
|
err_domain:
|
|
/* Should really dispose of the domain but... */
|
|
err_alloc:
|
|
kfree(d->type_buf);
|
|
kfree(d->type_buf_def);
|
|
kfree(d->wake_buf);
|
|
kfree(d->mask_buf_def);
|
|
kfree(d->mask_buf);
|
|
kfree(d->status_buf);
|
|
kfree(d->status_reg_buf);
|
|
kfree(d);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
|
|
|
|
/**
|
|
* regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
|
|
*
|
|
* @irq: Primary IRQ for the device
|
|
* @d: ®map_irq_chip_data allocated by regmap_add_irq_chip()
|
|
*
|
|
* This function also disposes of all mapped IRQs on the chip.
|
|
*/
|
|
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
|
|
{
|
|
unsigned int virq;
|
|
int hwirq;
|
|
|
|
if (!d)
|
|
return;
|
|
|
|
free_irq(irq, d);
|
|
|
|
/* Dispose all virtual irq from irq domain before removing it */
|
|
for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
|
|
/* Ignore hwirq if holes in the IRQ list */
|
|
if (!d->chip->irqs[hwirq].mask)
|
|
continue;
|
|
|
|
/*
|
|
* Find the virtual irq of hwirq on chip and if it is
|
|
* there then dispose it
|
|
*/
|
|
virq = irq_find_mapping(d->domain, hwirq);
|
|
if (virq)
|
|
irq_dispose_mapping(virq);
|
|
}
|
|
|
|
irq_domain_remove(d->domain);
|
|
kfree(d->type_buf);
|
|
kfree(d->type_buf_def);
|
|
kfree(d->wake_buf);
|
|
kfree(d->mask_buf_def);
|
|
kfree(d->mask_buf);
|
|
kfree(d->status_reg_buf);
|
|
kfree(d->status_buf);
|
|
kfree(d);
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
|
|
|
|
static void devm_regmap_irq_chip_release(struct device *dev, void *res)
|
|
{
|
|
struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
|
|
|
|
regmap_del_irq_chip(d->irq, d);
|
|
}
|
|
|
|
static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
|
|
|
|
{
|
|
struct regmap_irq_chip_data **r = res;
|
|
|
|
if (!r || !*r) {
|
|
WARN_ON(!r || !*r);
|
|
return 0;
|
|
}
|
|
return *r == data;
|
|
}
|
|
|
|
/**
|
|
* devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
|
|
*
|
|
* @dev: The device pointer on which irq_chip belongs to.
|
|
* @map: The regmap for the device.
|
|
* @irq: The IRQ the device uses to signal interrupts
|
|
* @irq_flags: The IRQF_ flags to use for the primary interrupt.
|
|
* @irq_base: Allocate at specific IRQ number if irq_base > 0.
|
|
* @chip: Configuration for the interrupt controller.
|
|
* @data: Runtime data structure for the controller, allocated on success
|
|
*
|
|
* Returns 0 on success or an errno on failure.
|
|
*
|
|
* The ®map_irq_chip_data will be automatically released when the device is
|
|
* unbound.
|
|
*/
|
|
int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
|
|
int irq_flags, int irq_base,
|
|
const struct regmap_irq_chip *chip,
|
|
struct regmap_irq_chip_data **data)
|
|
{
|
|
struct regmap_irq_chip_data **ptr, *d;
|
|
int ret;
|
|
|
|
ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
|
|
GFP_KERNEL);
|
|
if (!ptr)
|
|
return -ENOMEM;
|
|
|
|
ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
|
|
chip, &d);
|
|
if (ret < 0) {
|
|
devres_free(ptr);
|
|
return ret;
|
|
}
|
|
|
|
*ptr = d;
|
|
devres_add(dev, ptr);
|
|
*data = d;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
|
|
|
|
/**
|
|
* devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
|
|
*
|
|
* @dev: Device for which which resource was allocated.
|
|
* @irq: Primary IRQ for the device.
|
|
* @data: ®map_irq_chip_data allocated by regmap_add_irq_chip().
|
|
*
|
|
* A resource managed version of regmap_del_irq_chip().
|
|
*/
|
|
void devm_regmap_del_irq_chip(struct device *dev, int irq,
|
|
struct regmap_irq_chip_data *data)
|
|
{
|
|
int rc;
|
|
|
|
WARN_ON(irq != data->irq);
|
|
rc = devres_release(dev, devm_regmap_irq_chip_release,
|
|
devm_regmap_irq_chip_match, data);
|
|
|
|
if (rc != 0)
|
|
WARN_ON(rc);
|
|
}
|
|
EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
|
|
|
|
/**
|
|
* regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
|
|
*
|
|
* @data: regmap irq controller to operate on.
|
|
*
|
|
* Useful for drivers to request their own IRQs.
|
|
*/
|
|
int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
|
|
{
|
|
WARN_ON(!data->irq_base);
|
|
return data->irq_base;
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
|
|
|
|
/**
|
|
* regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
|
|
*
|
|
* @data: regmap irq controller to operate on.
|
|
* @irq: index of the interrupt requested in the chip IRQs.
|
|
*
|
|
* Useful for drivers to request their own IRQs.
|
|
*/
|
|
int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
|
|
{
|
|
/* Handle holes in the IRQ list */
|
|
if (!data->chip->irqs[irq].mask)
|
|
return -EINVAL;
|
|
|
|
return irq_create_mapping(data->domain, irq);
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
|
|
|
|
/**
|
|
* regmap_irq_get_domain() - Retrieve the irq_domain for the chip
|
|
*
|
|
* @data: regmap_irq controller to operate on.
|
|
*
|
|
* Useful for drivers to request their own IRQs and for integration
|
|
* with subsystems. For ease of integration NULL is accepted as a
|
|
* domain, allowing devices to just call this even if no domain is
|
|
* allocated.
|
|
*/
|
|
struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
|
|
{
|
|
if (data)
|
|
return data->domain;
|
|
else
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(regmap_irq_get_domain);
|