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![Greg Kroah-Hartman](/assets/img/avatar_default.png)
There were a few files in the regmap code that did not have SPDX identifiers on them, so fix that up. At the same time, remove the "free form" text that specified the license of the file, as that is impossible for any tool to properly parse. Also, as Mark loves // comment markers, convert all of the headers to be the same to make things look consistent :) Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Mark Brown <broonie@kernel.org>
379 lines
7.6 KiB
C
379 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Register map access API - MMIO support
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//
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// Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "internal.h"
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struct regmap_mmio_context {
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void __iomem *regs;
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unsigned val_bytes;
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bool attached_clk;
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struct clk *clk;
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void (*reg_write)(struct regmap_mmio_context *ctx,
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unsigned int reg, unsigned int val);
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unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
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unsigned int reg);
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};
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static int regmap_mmio_regbits_check(size_t reg_bits)
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{
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switch (reg_bits) {
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case 8:
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case 16:
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case 32:
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#ifdef CONFIG_64BIT
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case 64:
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#endif
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int regmap_mmio_get_min_stride(size_t val_bits)
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{
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int min_stride;
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switch (val_bits) {
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case 8:
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/* The core treats 0 as 1 */
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min_stride = 0;
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return 0;
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case 16:
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min_stride = 2;
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break;
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case 32:
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min_stride = 4;
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break;
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#ifdef CONFIG_64BIT
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case 64:
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min_stride = 8;
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break;
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#endif
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default:
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return -EINVAL;
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}
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return min_stride;
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}
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static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
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unsigned int reg,
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unsigned int val)
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{
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writeb(val, ctx->regs + reg);
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}
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static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
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unsigned int reg,
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unsigned int val)
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{
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writew(val, ctx->regs + reg);
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}
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static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
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unsigned int reg,
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unsigned int val)
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{
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iowrite16be(val, ctx->regs + reg);
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}
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static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
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unsigned int reg,
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unsigned int val)
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{
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writel(val, ctx->regs + reg);
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}
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static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
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unsigned int reg,
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unsigned int val)
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{
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iowrite32be(val, ctx->regs + reg);
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}
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#ifdef CONFIG_64BIT
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static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
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unsigned int reg,
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unsigned int val)
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{
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writeq(val, ctx->regs + reg);
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}
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#endif
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static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
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{
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struct regmap_mmio_context *ctx = context;
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int ret;
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if (!IS_ERR(ctx->clk)) {
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ret = clk_enable(ctx->clk);
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if (ret < 0)
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return ret;
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}
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ctx->reg_write(ctx, reg, val);
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if (!IS_ERR(ctx->clk))
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clk_disable(ctx->clk);
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return 0;
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}
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static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
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unsigned int reg)
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{
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return readb(ctx->regs + reg);
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}
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static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
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unsigned int reg)
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{
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return readw(ctx->regs + reg);
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}
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static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
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unsigned int reg)
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{
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return ioread16be(ctx->regs + reg);
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}
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static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
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unsigned int reg)
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{
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return readl(ctx->regs + reg);
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}
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static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
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unsigned int reg)
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{
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return ioread32be(ctx->regs + reg);
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}
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#ifdef CONFIG_64BIT
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static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
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unsigned int reg)
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{
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return readq(ctx->regs + reg);
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}
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#endif
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static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct regmap_mmio_context *ctx = context;
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int ret;
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if (!IS_ERR(ctx->clk)) {
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ret = clk_enable(ctx->clk);
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if (ret < 0)
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return ret;
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}
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*val = ctx->reg_read(ctx, reg);
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if (!IS_ERR(ctx->clk))
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clk_disable(ctx->clk);
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return 0;
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}
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static void regmap_mmio_free_context(void *context)
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{
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struct regmap_mmio_context *ctx = context;
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if (!IS_ERR(ctx->clk)) {
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clk_unprepare(ctx->clk);
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if (!ctx->attached_clk)
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clk_put(ctx->clk);
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}
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kfree(context);
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}
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static const struct regmap_bus regmap_mmio = {
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.fast_io = true,
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.reg_write = regmap_mmio_write,
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.reg_read = regmap_mmio_read,
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.free_context = regmap_mmio_free_context,
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.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
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};
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static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
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const char *clk_id,
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void __iomem *regs,
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const struct regmap_config *config)
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{
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struct regmap_mmio_context *ctx;
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int min_stride;
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int ret;
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ret = regmap_mmio_regbits_check(config->reg_bits);
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if (ret)
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return ERR_PTR(ret);
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if (config->pad_bits)
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return ERR_PTR(-EINVAL);
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min_stride = regmap_mmio_get_min_stride(config->val_bits);
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if (min_stride < 0)
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return ERR_PTR(min_stride);
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if (config->reg_stride < min_stride)
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return ERR_PTR(-EINVAL);
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return ERR_PTR(-ENOMEM);
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ctx->regs = regs;
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ctx->val_bytes = config->val_bits / 8;
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ctx->clk = ERR_PTR(-ENODEV);
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switch (regmap_get_val_endian(dev, ®map_mmio, config)) {
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case REGMAP_ENDIAN_DEFAULT:
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case REGMAP_ENDIAN_LITTLE:
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#ifdef __LITTLE_ENDIAN
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case REGMAP_ENDIAN_NATIVE:
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#endif
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switch (config->val_bits) {
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case 8:
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ctx->reg_read = regmap_mmio_read8;
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ctx->reg_write = regmap_mmio_write8;
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break;
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case 16:
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ctx->reg_read = regmap_mmio_read16le;
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ctx->reg_write = regmap_mmio_write16le;
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break;
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case 32:
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ctx->reg_read = regmap_mmio_read32le;
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ctx->reg_write = regmap_mmio_write32le;
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break;
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#ifdef CONFIG_64BIT
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case 64:
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ctx->reg_read = regmap_mmio_read64le;
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ctx->reg_write = regmap_mmio_write64le;
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break;
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#endif
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default:
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ret = -EINVAL;
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goto err_free;
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}
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break;
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case REGMAP_ENDIAN_BIG:
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#ifdef __BIG_ENDIAN
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case REGMAP_ENDIAN_NATIVE:
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#endif
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switch (config->val_bits) {
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case 8:
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ctx->reg_read = regmap_mmio_read8;
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ctx->reg_write = regmap_mmio_write8;
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break;
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case 16:
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ctx->reg_read = regmap_mmio_read16be;
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ctx->reg_write = regmap_mmio_write16be;
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break;
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case 32:
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ctx->reg_read = regmap_mmio_read32be;
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ctx->reg_write = regmap_mmio_write32be;
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break;
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default:
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ret = -EINVAL;
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goto err_free;
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}
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break;
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default:
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ret = -EINVAL;
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goto err_free;
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}
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if (clk_id == NULL)
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return ctx;
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ctx->clk = clk_get(dev, clk_id);
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if (IS_ERR(ctx->clk)) {
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ret = PTR_ERR(ctx->clk);
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goto err_free;
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}
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ret = clk_prepare(ctx->clk);
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if (ret < 0) {
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clk_put(ctx->clk);
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goto err_free;
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}
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return ctx;
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err_free:
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kfree(ctx);
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return ERR_PTR(ret);
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}
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struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
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void __iomem *regs,
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const struct regmap_config *config,
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struct lock_class_key *lock_key,
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const char *lock_name)
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{
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struct regmap_mmio_context *ctx;
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ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
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if (IS_ERR(ctx))
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return ERR_CAST(ctx);
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return __regmap_init(dev, ®map_mmio, ctx, config,
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lock_key, lock_name);
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}
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EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
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struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
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const char *clk_id,
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void __iomem *regs,
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const struct regmap_config *config,
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struct lock_class_key *lock_key,
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const char *lock_name)
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{
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struct regmap_mmio_context *ctx;
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ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
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if (IS_ERR(ctx))
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return ERR_CAST(ctx);
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return __devm_regmap_init(dev, ®map_mmio, ctx, config,
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lock_key, lock_name);
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}
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EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
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int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
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{
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struct regmap_mmio_context *ctx = map->bus_context;
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ctx->clk = clk;
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ctx->attached_clk = true;
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return clk_prepare(ctx->clk);
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}
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EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
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void regmap_mmio_detach_clk(struct regmap *map)
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{
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struct regmap_mmio_context *ctx = map->bus_context;
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clk_unprepare(ctx->clk);
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ctx->attached_clk = false;
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ctx->clk = NULL;
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}
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EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
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MODULE_LICENSE("GPL v2");
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