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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
201 lines
6 KiB
C
201 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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struct qcom_ipq806x_sata_phy {
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void __iomem *mmio;
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struct clk *cfg_clk;
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struct device *dev;
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};
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#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
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#define SATA_PHY_P0_PARAM0 0x200
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#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
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#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
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#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
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#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
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#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
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#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
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#define SATA_PHY_P0_PARAM1 0x204
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#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
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#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
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#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
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#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
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#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
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#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
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#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
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#define SATA_PHY_P0_PARAM2 0x208
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#define SATA_PHY_P0_PARAM2_RX_EQ(x) __set(x, 20, 18)
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#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
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#define SATA_PHY_P0_PARAM3 0x20C
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#define SATA_PHY_SSC_EN 0x8
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#define SATA_PHY_P0_PARAM4 0x210
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#define SATA_PHY_REF_SSP_EN 0x2
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#define SATA_PHY_RESET 0x1
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static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
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{
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struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
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u32 reg;
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/* Setting SSC_EN to 1 */
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
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reg = reg | SATA_PHY_SSC_EN;
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
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~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
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SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
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SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
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reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
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~(SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK |
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SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK |
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SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK);
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reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) |
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SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(0x55) |
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SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(0x55);
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) &
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~SATA_PHY_P0_PARAM2_RX_EQ_MASK;
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reg |= SATA_PHY_P0_PARAM2_RX_EQ(0x3);
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
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/* Setting PHY_RESET to 1 */
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
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reg = reg | SATA_PHY_RESET;
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
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/* Setting REF_SSP_EN to 1 */
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
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reg = reg | SATA_PHY_REF_SSP_EN | SATA_PHY_RESET;
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
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/* make sure all changes complete before we let the PHY out of reset */
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mb();
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/* sleep for max. 50us more to combine processor wakeups */
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usleep_range(20, 20 + 50);
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/* Clearing PHY_RESET to 0 */
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
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reg = reg & ~SATA_PHY_RESET;
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
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return 0;
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}
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static int qcom_ipq806x_sata_phy_exit(struct phy *generic_phy)
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{
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struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
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u32 reg;
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/* Setting PHY_RESET to 1 */
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reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
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reg = reg | SATA_PHY_RESET;
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writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
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return 0;
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}
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static const struct phy_ops qcom_ipq806x_sata_phy_ops = {
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.init = qcom_ipq806x_sata_phy_init,
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.exit = qcom_ipq806x_sata_phy_exit,
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.owner = THIS_MODULE,
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};
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static int qcom_ipq806x_sata_phy_probe(struct platform_device *pdev)
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{
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struct qcom_ipq806x_sata_phy *phy;
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct phy_provider *phy_provider;
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struct phy *generic_phy;
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int ret;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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phy->mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(phy->mmio))
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return PTR_ERR(phy->mmio);
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generic_phy = devm_phy_create(dev, NULL, &qcom_ipq806x_sata_phy_ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "%s: failed to create phy\n", __func__);
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return PTR_ERR(generic_phy);
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}
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phy->dev = dev;
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phy_set_drvdata(generic_phy, phy);
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platform_set_drvdata(pdev, phy);
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phy->cfg_clk = devm_clk_get(dev, "cfg");
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if (IS_ERR(phy->cfg_clk)) {
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dev_err(dev, "Failed to get sata cfg clock\n");
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return PTR_ERR(phy->cfg_clk);
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}
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ret = clk_prepare_enable(phy->cfg_clk);
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if (ret)
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return ret;
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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clk_disable_unprepare(phy->cfg_clk);
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dev_err(dev, "%s: failed to register phy\n", __func__);
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return PTR_ERR(phy_provider);
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}
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return 0;
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}
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static int qcom_ipq806x_sata_phy_remove(struct platform_device *pdev)
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{
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struct qcom_ipq806x_sata_phy *phy = platform_get_drvdata(pdev);
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clk_disable_unprepare(phy->cfg_clk);
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return 0;
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}
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static const struct of_device_id qcom_ipq806x_sata_phy_of_match[] = {
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{ .compatible = "qcom,ipq806x-sata-phy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, qcom_ipq806x_sata_phy_of_match);
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static struct platform_driver qcom_ipq806x_sata_phy_driver = {
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.probe = qcom_ipq806x_sata_phy_probe,
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.remove = qcom_ipq806x_sata_phy_remove,
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.driver = {
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.name = "qcom-ipq806x-sata-phy",
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.of_match_table = qcom_ipq806x_sata_phy_of_match,
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}
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};
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module_platform_driver(qcom_ipq806x_sata_phy_driver);
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MODULE_DESCRIPTION("QCOM IPQ806x SATA PHY driver");
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MODULE_LICENSE("GPL v2");
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