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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
226 lines
5.7 KiB
C
226 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*/
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#include "phy-qcom-ufs-qmp-20nm.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_20nm"
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static
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int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
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int tbl_size_A, tbl_size_B;
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u8 major = ufs_qcom_phy->host_ctrl_rev_major;
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u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
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u16 step = ufs_qcom_phy->host_ctrl_rev_step;
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int err;
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if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
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tbl_A = phy_cal_table_rate_A_1_2_0;
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} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
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tbl_A = phy_cal_table_rate_A_1_3_0;
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} else {
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dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
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__func__);
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err = -ENODEV;
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goto out;
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}
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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tbl_B = phy_cal_table_rate_B;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
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tbl_B, tbl_size_B, is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
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{
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phy_common->quirks =
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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}
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static
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int ufs_qcom_phy_qmp_20nm_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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phy_common->mode = PHY_MODE_INVALID;
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if (mode > 0)
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phy_common->mode = mode;
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return 0;
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}
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static
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void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
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{
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bool hibern8_exit_after_pwr_collapse = phy->quirks &
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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if (val) {
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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if (hibern8_exit_after_pwr_collapse) {
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/*
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* Give atleast 1us delay after restoring PHY analog
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* power.
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*/
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usleep_range(1, 2);
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writel_relaxed(0x0A, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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writel_relaxed(0x08, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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/*
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* Make sure workaround is deactivated before proceeding
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* with normal PHY operations.
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*/
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mb();
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}
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} else {
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if (hibern8_exit_after_pwr_collapse) {
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writel_relaxed(0x0A, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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writel_relaxed(0x02, phy->mmio +
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QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
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/*
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* Make sure that above workaround is activated before
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* PHY analog power collapse.
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*/
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mb();
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}
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* ensure that PHY knows its PHY analog rail is going
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* to be powered down
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*/
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mb();
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}
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}
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static
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void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
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phy->mmio + UFS_PHY_TX_LANE_ENABLE);
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mb();
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}
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static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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mb();
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}
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static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.set_mode = ufs_qcom_phy_qmp_20nm_set_mode,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
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.calibrate = ufs_qcom_phy_qmp_20nm_phy_calibrate,
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.start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
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.power_control = ufs_qcom_phy_qmp_20nm_power_control,
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};
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static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_20nm *phy;
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struct ufs_qcom_phy *phy_common;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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phy_common = &phy->common_cfg;
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generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
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&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
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if (!generic_phy) {
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err = -EIO;
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goto out;
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}
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err = ufs_qcom_phy_init_clks(phy_common);
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if (err)
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goto out;
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err = ufs_qcom_phy_init_vregulators(phy_common);
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if (err)
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goto out;
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ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
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out:
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-20nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
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.probe = ufs_qcom_phy_qmp_20nm_probe,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
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.name = "ufs_qcom_phy_qmp_20nm",
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
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MODULE_LICENSE("GPL v2");
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