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cafc0eab16
Enable support for IRQ stacks on !MMU, and add the code to the IRQ entry path to switch to the IRQ stack if not running from it already. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
160 lines
3.7 KiB
ArmAsm
160 lines
3.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/kernel/entry-v7m.S
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*
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* Copyright (C) 2008 ARM Ltd.
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*
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* Low-level vector interface routines for the ARMv7-M architecture
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*/
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#include <asm/memory.h>
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#include <asm/glue.h>
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#include <asm/thread_notify.h>
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#include <asm/v7m.h>
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#include "entry-header.S"
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#ifdef CONFIG_TRACE_IRQFLAGS
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#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
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#endif
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__invalid_entry:
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v7m_exception_entry
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#ifdef CONFIG_PRINTK
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adr r0, strerr
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mrs r1, ipsr
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mov r2, lr
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bl _printk
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#endif
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mov r0, sp
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bl show_regs
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1: b 1b
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ENDPROC(__invalid_entry)
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strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
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.align 2
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__irq_entry:
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v7m_exception_entry
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@
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@ Invoke the IRQ handler
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@
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mov r0, sp
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ldr_this_cpu sp, irq_stack_ptr, r1, r2
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@
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@ If we took the interrupt while running in the kernel, we may already
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@ be using the IRQ stack, so revert to the original value in that case.
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@
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subs r2, sp, r0 @ SP above bottom of IRQ stack?
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rsbscs r2, r2, #THREAD_SIZE @ ... and below the top?
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movcs sp, r0
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push {r0, lr} @ preserve LR and original SP
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@ routine called with r0 = struct pt_regs *
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bl generic_handle_arch_irq
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pop {r0, lr}
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mov sp, r0
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@
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@ Check for any pending work if returning to user
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@
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ldr r1, =BASEADDR_V7M_SCB
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ldr r0, [r1, V7M_SCB_ICSR]
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tst r0, V7M_SCB_ICSR_RETTOBASE
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beq 2f
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get_thread_info tsk
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ldr r2, [tsk, #TI_FLAGS]
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movs r2, r2, lsl #16
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beq 2f @ no work pending
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mov r0, #V7M_SCB_ICSR_PENDSVSET
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str r0, [r1, V7M_SCB_ICSR] @ raise PendSV
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2:
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@ registers r0-r3 and r12 are automatically restored on exception
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@ return. r4-r7 were not clobbered in v7m_exception_entry so for
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@ correctness they don't need to be restored. So only r8-r11 must be
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@ restored here. The easiest way to do so is to restore r0-r7, too.
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ldmia sp!, {r0-r11}
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add sp, #PT_REGS_SIZE-S_IP
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cpsie i
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bx lr
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ENDPROC(__irq_entry)
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__pendsv_entry:
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v7m_exception_entry
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ldr r1, =BASEADDR_V7M_SCB
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mov r0, #V7M_SCB_ICSR_PENDSVCLR
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str r0, [r1, V7M_SCB_ICSR] @ clear PendSV
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@ execute the pending work, including reschedule
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get_thread_info tsk
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mov why, #0
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b ret_to_user_from_irq
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ENDPROC(__pendsv_entry)
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/*
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* Register switch for ARMv7-M processors.
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* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
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* previous and next are guaranteed not to be the same.
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*/
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ENTRY(__switch_to)
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.fnstart
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.cantunwind
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add ip, r1, #TI_CPU_SAVE
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stmia ip!, {r4 - r11} @ Store most regs on stack
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str sp, [ip], #4
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str lr, [ip], #4
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mov r5, r0
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mov r6, r2 @ Preserve 'next'
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add r4, r2, #TI_CPU_SAVE
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ldr r0, =thread_notify_head
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mov r1, #THREAD_NOTIFY_SWITCH
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bl atomic_notifier_call_chain
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mov r0, r5
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mov r1, r6
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ldmia r4, {r4 - r12, lr} @ Load all regs saved previously
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set_current r1, r2
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mov sp, ip
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bx lr
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.fnend
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ENDPROC(__switch_to)
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.data
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#if CONFIG_CPU_V7M_NUM_IRQ <= 112
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.align 9
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#else
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.align 10
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#endif
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/*
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* Vector table (Natural alignment need to be ensured)
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*/
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ENTRY(vector_table)
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.long 0 @ 0 - Reset stack pointer
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.long __invalid_entry @ 1 - Reset
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.long __invalid_entry @ 2 - NMI
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.long __invalid_entry @ 3 - HardFault
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.long __invalid_entry @ 4 - MemManage
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.long __invalid_entry @ 5 - BusFault
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.long __invalid_entry @ 6 - UsageFault
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.long __invalid_entry @ 7 - Reserved
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.long __invalid_entry @ 8 - Reserved
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.long __invalid_entry @ 9 - Reserved
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.long __invalid_entry @ 10 - Reserved
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.long vector_swi @ 11 - SVCall
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.long __invalid_entry @ 12 - Debug Monitor
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.long __invalid_entry @ 13 - Reserved
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.long __pendsv_entry @ 14 - PendSV
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.long __invalid_entry @ 15 - SysTick
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.rept CONFIG_CPU_V7M_NUM_IRQ
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.long __irq_entry @ External Interrupts
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.endr
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.align 2
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.globl exc_ret
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exc_ret:
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.space 4
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