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6bd33e1ece
The kernel runs in M-mode without using page tables, and thus can't run bare metal without help from additional firmware. Most of the patch is just stubbing out code not needed without page tables, but there is an interesting detail in the signals implementation: - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO entry point, but the ELF VDSO is not supported for nommu Linux. We instead copy the code to call the syscall onto the stack. In addition to enabling the nommu code a new defconfig for a small kernel image that can run in nommu mode on qemu is also provided, to run a kernel in qemu you can use the following command line: qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \ -kernel arch/riscv/boot/loader \ -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards around PCI_IOBASE definition to fix build issues; fixed checkpatch issues; move the PCI_IO_* and VMEMMAP address space macros along with the others; resolve sparse warning] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/mm.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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/*
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* When necessary, performs a deferred icache flush for the given MM context,
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* on the local CPU. RISC-V has no direct mechanism for instruction cache
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* shoot downs, so instead we send an IPI that informs the remote harts they
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* need to flush their local instruction caches. To avoid pathologically slow
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* behavior in a common case (a bunch of single-hart processes on a many-hart
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* machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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* executing a MM context and instead schedule a deferred local instruction
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* cache flush to be performed before execution resumes on each hart. This
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* actually performs that local instruction cache flush, which implicitly only
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* refers to the current hart.
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*/
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static inline void flush_icache_deferred(struct mm_struct *mm)
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{
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#ifdef CONFIG_SMP
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unsigned int cpu = smp_processor_id();
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cpumask_t *mask = &mm->context.icache_stale_mask;
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if (cpumask_test_cpu(cpu, mask)) {
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cpumask_clear_cpu(cpu, mask);
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/*
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* Ensure the remote hart's writes are visible to this hart.
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* This pairs with a barrier in flush_icache_mm.
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*/
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smp_mb();
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local_flush_icache_all();
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}
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#endif
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}
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void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *task)
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{
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unsigned int cpu;
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if (unlikely(prev == next))
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return;
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/*
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* Mark the current MM context as inactive, and the next as
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* active. This is at least used by the icache flushing
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* routines in order to determine who should be flushed.
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*/
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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#ifdef CONFIG_MMU
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csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE);
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local_flush_tlb_all();
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#endif
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flush_icache_deferred(next);
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}
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