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![Sebastian Hesselbarth](/assets/img/avatar_default.png)
Marvell mdio driver uses internal registers that can be clock gated on some SoCs. This patch just adds optional clock handling, to allow to pass and enable the corresponding clock. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
309 lines
7.2 KiB
C
309 lines
7.2 KiB
C
/*
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* Driver for the MDIO interface of Marvell network interfaces.
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*
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* Since the MDIO interface of Marvell network interfaces is shared
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* between all network interfaces, having a single driver allows to
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* handle concurrent accesses properly (you may have four Ethernet
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* ports, but they in fact share the same SMI interface to access the
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* MDIO bus). Moreover, this MDIO interface code is similar between
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* the mv643xx_eth driver and the mvneta driver. For now, it is only
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* used by the mvneta driver, but it could later be used by the
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* mv643xx_eth driver as well.
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/phy.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/of_mdio.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#define MVMDIO_SMI_DATA_SHIFT 0
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#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
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#define MVMDIO_SMI_PHY_REG_SHIFT 21
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#define MVMDIO_SMI_READ_OPERATION BIT(26)
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#define MVMDIO_SMI_WRITE_OPERATION 0
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#define MVMDIO_SMI_READ_VALID BIT(27)
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#define MVMDIO_SMI_BUSY BIT(28)
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#define MVMDIO_ERR_INT_CAUSE 0x007C
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#define MVMDIO_ERR_INT_SMI_DONE 0x00000010
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#define MVMDIO_ERR_INT_MASK 0x0080
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struct orion_mdio_dev {
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struct mutex lock;
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void __iomem *regs;
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struct clk *clk;
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/*
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* If we have access to the error interrupt pin (which is
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* somewhat misnamed as it not only reflects internal errors
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* but also reflects SMI completion), use that to wait for
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* SMI access completion instead of polling the SMI busy bit.
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*/
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int err_interrupt;
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wait_queue_head_t smi_busy_wait;
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};
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static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
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{
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return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
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}
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/* Wait for the SMI unit to be ready for another operation
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*/
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static int orion_mdio_wait_ready(struct mii_bus *bus)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int count;
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if (dev->err_interrupt <= 0) {
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count = 0;
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while (1) {
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if (orion_mdio_smi_is_done(dev))
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break;
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if (count > 100) {
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dev_err(bus->parent,
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"Timeout: SMI busy for too long\n");
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return -ETIMEDOUT;
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}
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udelay(10);
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count++;
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}
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} else {
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if (!orion_mdio_smi_is_done(dev)) {
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wait_event_timeout(dev->smi_busy_wait,
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orion_mdio_smi_is_done(dev),
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msecs_to_jiffies(100));
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if (!orion_mdio_smi_is_done(dev))
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int orion_mdio_read(struct mii_bus *bus, int mii_id,
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int regnum)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int count;
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u32 val;
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int ret;
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mutex_lock(&dev->lock);
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ret = orion_mdio_wait_ready(bus);
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if (ret < 0) {
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mutex_unlock(&dev->lock);
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return ret;
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}
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writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_READ_OPERATION),
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dev->regs);
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/* Wait for the value to become available */
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count = 0;
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while (1) {
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val = readl(dev->regs);
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if (val & MVMDIO_SMI_READ_VALID)
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break;
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if (count > 100) {
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dev_err(bus->parent, "Timeout when reading PHY\n");
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mutex_unlock(&dev->lock);
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return -ETIMEDOUT;
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}
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udelay(10);
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count++;
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}
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mutex_unlock(&dev->lock);
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return val & 0xFFFF;
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}
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static int orion_mdio_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int ret;
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mutex_lock(&dev->lock);
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ret = orion_mdio_wait_ready(bus);
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if (ret < 0) {
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mutex_unlock(&dev->lock);
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return ret;
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}
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writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_WRITE_OPERATION |
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(value << MVMDIO_SMI_DATA_SHIFT)),
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dev->regs);
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mutex_unlock(&dev->lock);
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return 0;
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}
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static int orion_mdio_reset(struct mii_bus *bus)
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{
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return 0;
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}
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static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
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{
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struct orion_mdio_dev *dev = dev_id;
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if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
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MVMDIO_ERR_INT_SMI_DONE) {
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writel(~MVMDIO_ERR_INT_SMI_DONE,
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dev->regs + MVMDIO_ERR_INT_CAUSE);
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wake_up(&dev->smi_busy_wait);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int orion_mdio_probe(struct platform_device *pdev)
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{
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struct resource *r;
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struct mii_bus *bus;
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struct orion_mdio_dev *dev;
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int i, ret;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "No SMI register address given\n");
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return -ENODEV;
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}
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bus = mdiobus_alloc_size(sizeof(struct orion_mdio_dev));
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if (!bus) {
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dev_err(&pdev->dev, "Cannot allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->name = "orion_mdio_bus";
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bus->read = orion_mdio_read;
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bus->write = orion_mdio_write;
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bus->reset = orion_mdio_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
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dev_name(&pdev->dev));
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bus->parent = &pdev->dev;
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bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
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if (!bus->irq) {
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mdiobus_free(bus);
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return -ENOMEM;
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}
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for (i = 0; i < PHY_MAX_ADDR; i++)
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bus->irq[i] = PHY_POLL;
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dev = bus->priv;
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dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!dev->regs) {
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dev_err(&pdev->dev, "Unable to remap SMI register\n");
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ret = -ENODEV;
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goto out_mdio;
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}
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init_waitqueue_head(&dev->smi_busy_wait);
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dev->clk = devm_clk_get(&pdev->dev, NULL);
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if (!IS_ERR(dev->clk))
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clk_prepare_enable(dev->clk);
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dev->err_interrupt = platform_get_irq(pdev, 0);
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if (dev->err_interrupt != -ENXIO) {
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ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
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orion_mdio_err_irq,
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IRQF_SHARED, pdev->name, dev);
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if (ret)
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goto out_mdio;
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writel(MVMDIO_ERR_INT_SMI_DONE,
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dev->regs + MVMDIO_ERR_INT_MASK);
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}
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mutex_init(&dev->lock);
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if (pdev->dev.of_node)
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ret = of_mdiobus_register(bus, pdev->dev.of_node);
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else
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ret = mdiobus_register(bus);
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if (ret < 0) {
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dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
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goto out_mdio;
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}
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platform_set_drvdata(pdev, bus);
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return 0;
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out_mdio:
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if (!IS_ERR(dev->clk))
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clk_disable_unprepare(dev->clk);
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kfree(bus->irq);
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mdiobus_free(bus);
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return ret;
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}
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static int orion_mdio_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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struct orion_mdio_dev *dev = bus->priv;
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writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
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mdiobus_unregister(bus);
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kfree(bus->irq);
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mdiobus_free(bus);
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if (!IS_ERR(dev->clk))
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clk_disable_unprepare(dev->clk);
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return 0;
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}
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static const struct of_device_id orion_mdio_match[] = {
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{ .compatible = "marvell,orion-mdio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, orion_mdio_match);
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static struct platform_driver orion_mdio_driver = {
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.probe = orion_mdio_probe,
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.remove = orion_mdio_remove,
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.driver = {
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.name = "orion-mdio",
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.of_match_table = orion_mdio_match,
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},
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};
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module_platform_driver(orion_mdio_driver);
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MODULE_DESCRIPTION("Marvell MDIO interface driver");
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MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:orion-mdio");
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