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![Sascha Hauer](/assets/img/avatar_default.png)
The IPU is the Image Processing Unit found on i.MX51/53/6 SoCs. It features several units for image processing, this patch adds support for the units needed for Framebuffer support, namely: - Display Controller (dc) - Display Interface (di) - Display Multi Fifo Controller (dmfc) - Display Processor (dp) - Image DMA Controller (idmac) This patch is based on the Freescale driver, but follows a different approach. The Freescale code implements logical idmac channels and the handling of the subunits is hidden in common idmac code pathes in big switch/case statements. This patch instead just provides code and resource management for the different subunits. The user, in this case the framebuffer driver, decides how the different units play together. The IPU has other units missing in this patch: - CMOS Sensor Interface (csi) - Video Deinterlacer (vdi) - Sensor Multi FIFO Controler (smfc) - Image Converter (ic) - Image Rotator (irt) Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
408 lines
8.9 KiB
C
408 lines
8.9 KiB
C
/*
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* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include "imx-ipu-v3.h"
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#include "ipu-prv.h"
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#define DMFC_RD_CHAN 0x0000
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#define DMFC_WR_CHAN 0x0004
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#define DMFC_WR_CHAN_DEF 0x0008
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#define DMFC_DP_CHAN 0x000c
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#define DMFC_DP_CHAN_DEF 0x0010
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#define DMFC_GENERAL1 0x0014
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#define DMFC_GENERAL2 0x0018
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#define DMFC_IC_CTRL 0x001c
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#define DMFC_STAT 0x0020
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#define DMFC_WR_CHAN_1_28 0
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#define DMFC_WR_CHAN_2_41 8
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#define DMFC_WR_CHAN_1C_42 16
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#define DMFC_WR_CHAN_2C_43 24
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#define DMFC_DP_CHAN_5B_23 0
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#define DMFC_DP_CHAN_5F_27 8
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#define DMFC_DP_CHAN_6B_24 16
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#define DMFC_DP_CHAN_6F_29 24
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#define DMFC_FIFO_SIZE_64 (3 << 3)
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#define DMFC_FIFO_SIZE_128 (2 << 3)
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#define DMFC_FIFO_SIZE_256 (1 << 3)
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#define DMFC_FIFO_SIZE_512 (0 << 3)
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#define DMFC_SEGMENT(x) ((x & 0x7) << 0)
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#define DMFC_BURSTSIZE_128 (0 << 6)
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#define DMFC_BURSTSIZE_64 (1 << 6)
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#define DMFC_BURSTSIZE_32 (2 << 6)
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#define DMFC_BURSTSIZE_16 (3 << 6)
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struct dmfc_channel_data {
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int ipu_channel;
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unsigned long channel_reg;
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unsigned long shift;
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unsigned eot_shift;
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unsigned max_fifo_lines;
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};
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static const struct dmfc_channel_data dmfcdata[] = {
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{
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.ipu_channel = 23,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_5B_23,
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.eot_shift = 20,
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.max_fifo_lines = 3,
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}, {
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.ipu_channel = 24,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_6B_24,
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.eot_shift = 22,
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.max_fifo_lines = 1,
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}, {
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.ipu_channel = 27,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_5F_27,
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.eot_shift = 21,
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.max_fifo_lines = 2,
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}, {
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.ipu_channel = 28,
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.channel_reg = DMFC_WR_CHAN,
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.shift = DMFC_WR_CHAN_1_28,
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.eot_shift = 16,
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.max_fifo_lines = 2,
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}, {
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.ipu_channel = 29,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_6F_29,
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.eot_shift = 23,
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.max_fifo_lines = 1,
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},
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};
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#define DMFC_NUM_CHANNELS ARRAY_SIZE(dmfcdata)
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struct ipu_dmfc_priv;
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struct dmfc_channel {
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unsigned slots;
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unsigned slotmask;
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unsigned segment;
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int burstsize;
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struct ipu_soc *ipu;
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struct ipu_dmfc_priv *priv;
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const struct dmfc_channel_data *data;
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};
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struct ipu_dmfc_priv {
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struct ipu_soc *ipu;
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struct device *dev;
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struct dmfc_channel channels[DMFC_NUM_CHANNELS];
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struct mutex mutex;
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unsigned long bandwidth_per_slot;
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void __iomem *base;
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int use_count;
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};
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int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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mutex_lock(&priv->mutex);
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if (!priv->use_count)
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ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
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priv->use_count++;
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mutex_unlock(&priv->mutex);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
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void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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mutex_lock(&priv->mutex);
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priv->use_count--;
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if (!priv->use_count)
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ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
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if (priv->use_count < 0)
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priv->use_count = 0;
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mutex_unlock(&priv->mutex);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
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static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
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int segment, int burstsize)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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u32 val, field;
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dev_dbg(priv->dev,
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"dmfc: using %d slots starting from segment %d for IPU channel %d\n",
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slots, segment, dmfc->data->ipu_channel);
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if (!dmfc)
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return -EINVAL;
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switch (slots) {
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case 1:
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field = DMFC_FIFO_SIZE_64;
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break;
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case 2:
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field = DMFC_FIFO_SIZE_128;
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break;
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case 4:
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field = DMFC_FIFO_SIZE_256;
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break;
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case 8:
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field = DMFC_FIFO_SIZE_512;
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break;
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default:
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return -EINVAL;
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}
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switch (burstsize) {
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case 16:
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field |= DMFC_BURSTSIZE_16;
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break;
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case 32:
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field |= DMFC_BURSTSIZE_32;
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break;
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case 64:
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field |= DMFC_BURSTSIZE_64;
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break;
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case 128:
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field |= DMFC_BURSTSIZE_128;
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break;
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}
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field |= DMFC_SEGMENT(segment);
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val = readl(priv->base + dmfc->data->channel_reg);
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val &= ~(0xff << dmfc->data->shift);
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val |= field << dmfc->data->shift;
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writel(val, priv->base + dmfc->data->channel_reg);
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dmfc->slots = slots;
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dmfc->segment = segment;
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dmfc->burstsize = burstsize;
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dmfc->slotmask = ((1 << slots) - 1) << segment;
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return 0;
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}
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static int dmfc_bandwidth_to_slots(struct ipu_dmfc_priv *priv,
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unsigned long bandwidth)
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{
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int slots = 1;
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while (slots * priv->bandwidth_per_slot < bandwidth)
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slots *= 2;
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return slots;
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}
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static int dmfc_find_slots(struct ipu_dmfc_priv *priv, int slots)
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{
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unsigned slotmask_need, slotmask_used = 0;
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int i, segment = 0;
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slotmask_need = (1 << slots) - 1;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++)
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slotmask_used |= priv->channels[i].slotmask;
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while (slotmask_need <= 0xff) {
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if (!(slotmask_used & slotmask_need))
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return segment;
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slotmask_need <<= 1;
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segment++;
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}
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return -EBUSY;
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}
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void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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int i;
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dev_dbg(priv->dev, "dmfc: freeing %d slots starting from segment %d\n",
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dmfc->slots, dmfc->segment);
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mutex_lock(&priv->mutex);
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if (!dmfc->slots)
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goto out;
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dmfc->slotmask = 0;
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dmfc->slots = 0;
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dmfc->segment = 0;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++)
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priv->channels[i].slotmask = 0;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
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if (priv->channels[i].slots > 0) {
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priv->channels[i].segment =
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dmfc_find_slots(priv, priv->channels[i].slots);
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priv->channels[i].slotmask =
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((1 << priv->channels[i].slots) - 1) <<
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priv->channels[i].segment;
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}
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}
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for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
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if (priv->channels[i].slots > 0)
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ipu_dmfc_setup_channel(&priv->channels[i],
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priv->channels[i].slots,
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priv->channels[i].segment,
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priv->channels[i].burstsize);
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}
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out:
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mutex_unlock(&priv->mutex);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);
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int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
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unsigned long bandwidth_pixel_per_second, int burstsize)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
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int segment = 0, ret = 0;
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dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
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bandwidth_pixel_per_second / 1000000,
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dmfc->data->ipu_channel);
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ipu_dmfc_free_bandwidth(dmfc);
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mutex_lock(&priv->mutex);
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if (slots > 8) {
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ret = -EBUSY;
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goto out;
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}
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segment = dmfc_find_slots(priv, slots);
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if (segment < 0) {
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ret = -EBUSY;
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goto out;
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}
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ipu_dmfc_setup_channel(dmfc, slots, segment, burstsize);
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out:
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mutex_unlock(&priv->mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);
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int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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u32 dmfc_gen1;
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dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
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if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
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dmfc_gen1 |= 1 << dmfc->data->eot_shift;
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else
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dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
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writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel);
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struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
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{
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struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
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int i;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++)
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if (dmfcdata[i].ipu_channel == ipu_channel)
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return &priv->channels[i];
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return ERR_PTR(-ENODEV);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_get);
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void ipu_dmfc_put(struct dmfc_channel *dmfc)
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{
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ipu_dmfc_free_bandwidth(dmfc);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_put);
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int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
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struct clk *ipu_clk)
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{
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struct ipu_dmfc_priv *priv;
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int i;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_ioremap(dev, base, PAGE_SIZE);
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if (!priv->base)
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return -ENOMEM;
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priv->dev = dev;
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priv->ipu = ipu;
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mutex_init(&priv->mutex);
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ipu->dmfc_priv = priv;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
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priv->channels[i].priv = priv;
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priv->channels[i].ipu = ipu;
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priv->channels[i].data = &dmfcdata[i];
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}
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writel(0x0, priv->base + DMFC_WR_CHAN);
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writel(0x0, priv->base + DMFC_DP_CHAN);
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/*
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* We have a total bandwidth of clkrate * 4pixel divided
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* into 8 slots.
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*/
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priv->bandwidth_per_slot = clk_get_rate(ipu_clk) / 8;
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dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
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priv->bandwidth_per_slot / 1000000);
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writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
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writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
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writel(0x00000003, priv->base + DMFC_GENERAL1);
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return 0;
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}
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void ipu_dmfc_exit(struct ipu_soc *ipu)
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{
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}
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