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![Omar Ramirez Luna](/assets/img/avatar_default.png)
This should get rid of warnings of the type: warning: passing argument 1 of '' discards qualifiers from pointer target type note: expected 'void *' but argument is of type 'const void *' Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
160 lines
3.7 KiB
C
160 lines
3.7 KiB
C
/*
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* hw_mmu.h
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* MMU types and API declarations
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef _HW_MMU_H
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#define _HW_MMU_H
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#include <linux/types.h>
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/* Bitmasks for interrupt sources */
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#define HW_MMU_TRANSLATION_FAULT 0x2
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#define HW_MMU_ALL_INTERRUPTS 0x1F
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#define HW_MMU_COARSE_PAGE_SIZE 0x400
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/* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow
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CPU/TLB Element size */
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enum hw_mmu_mixed_size_t {
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HW_MMU_TLBES,
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HW_MMU_CPUES
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};
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/* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */
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struct hw_mmu_map_attrs_t {
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enum hw_endianism_t endianism;
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enum hw_element_size_t element_size;
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enum hw_mmu_mixed_size_t mixed_size;
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bool donotlockmpupage;
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};
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extern hw_status hw_mmu_enable(void __iomem *base_address);
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extern hw_status hw_mmu_disable(void __iomem *base_address);
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extern hw_status hw_mmu_num_locked_set(void __iomem *base_address,
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u32 num_locked_entries);
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extern hw_status hw_mmu_victim_num_set(void __iomem *base_address,
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u32 victim_entry_num);
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/* For MMU faults */
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extern hw_status hw_mmu_event_ack(void __iomem *base_address,
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u32 irq_mask);
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extern hw_status hw_mmu_event_disable(void __iomem *base_address,
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u32 irq_mask);
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extern hw_status hw_mmu_event_enable(void __iomem *base_address,
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u32 irq_mask);
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extern hw_status hw_mmu_event_status(void __iomem *base_address,
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u32 *irq_mask);
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extern hw_status hw_mmu_fault_addr_read(void __iomem *base_address,
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u32 *addr);
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/* Set the TT base address */
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extern hw_status hw_mmu_ttb_set(void __iomem *base_address,
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u32 ttb_phys_addr);
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extern hw_status hw_mmu_twl_enable(void __iomem *base_address);
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extern hw_status hw_mmu_twl_disable(void __iomem *base_address);
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extern hw_status hw_mmu_tlb_add(void __iomem *base_address,
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u32 physical_addr,
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u32 virtual_addr,
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u32 page_sz,
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u32 entry_num,
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struct hw_mmu_map_attrs_t *map_attrs,
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s8 preserved_bit, s8 valid_bit);
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/* For PTEs */
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extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
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u32 physical_addr,
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u32 virtual_addr,
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u32 page_sz,
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struct hw_mmu_map_attrs_t *map_attrs);
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extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
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u32 virtual_addr, u32 page_size);
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void hw_mmu_tlb_flush_all(void __iomem *base);
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static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
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{
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u32 pte_addr;
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u32 va31_to20;
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va31_to20 = va >> (20 - 2); /* Left-shift by 2 here itself */
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va31_to20 &= 0xFFFFFFFCUL;
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pte_addr = l1_base + va31_to20;
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return pte_addr;
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}
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static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va)
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{
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u32 pte_addr;
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pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
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return pte_addr;
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}
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static inline u32 hw_mmu_pte_coarse_l1(u32 pte_val)
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{
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u32 pte_coarse;
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pte_coarse = pte_val & 0xFFFFFC00;
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return pte_coarse;
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}
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static inline u32 hw_mmu_pte_size_l1(u32 pte_val)
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{
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u32 pte_size = 0;
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if ((pte_val & 0x3) == 0x1) {
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/* Points to L2 PT */
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pte_size = HW_MMU_COARSE_PAGE_SIZE;
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}
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if ((pte_val & 0x3) == 0x2) {
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if (pte_val & (1 << 18))
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pte_size = HW_PAGE_SIZE16MB;
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else
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pte_size = HW_PAGE_SIZE1MB;
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}
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return pte_size;
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}
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static inline u32 hw_mmu_pte_size_l2(u32 pte_val)
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{
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u32 pte_size = 0;
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if (pte_val & 0x2)
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pte_size = HW_PAGE_SIZE4KB;
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else if (pte_val & 0x1)
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pte_size = HW_PAGE_SIZE64KB;
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return pte_size;
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}
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#endif /* _HW_MMU_H */
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