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94b63eb6e1
We'd like all architectures to convert to ARCH_ATOMIC, as once all
architectures are converted it will be possible to make significant
cleanups to the atomics headers, and this will make it much easier to
generically enable atomic functionality (e.g. debug logic in the
instrumented wrappers).
As a step towards that, this patch migrates hexagon to ARCH_ATOMIC. The
arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common
code wraps these with optional instrumentation to provide the regular
functions.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Brian Cain <bcain@codeaurora.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210525140232.53872-19-mark.rutland@arm.com
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* xchg/cmpxchg operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_CMPXCHG_H
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#define _ASM_CMPXCHG_H
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/*
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* __xchg - atomically exchange a register and a memory location
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* @x: value to swap
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* @ptr: pointer to memory
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* @size: size of the value
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*
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* Only 4 bytes supported currently.
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*
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* Note: there was an errata for V2 about .new's and memw_locked.
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*
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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unsigned long retval;
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/* Can't seem to use printk or panic here, so just stop */
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if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
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__asm__ __volatile__ (
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"1: %0 = memw_locked(%1);\n" /* load into retval */
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" memw_locked(%1,P0) = %2;\n" /* store into memory */
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" if (!P0) jump 1b;\n"
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: "=&r" (retval)
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: "r" (ptr), "r" (x)
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: "memory", "p0"
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);
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return retval;
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}
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/*
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* Atomically swap the contents of a register with memory. Should be atomic
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* between multiple CPU's and within interrupts on the same CPU.
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*/
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#define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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/*
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* see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
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* looks just like atomic_cmpxchg on our arch currently with a bunch of
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* variable casting.
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*/
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#define arch_cmpxchg(ptr, old, new) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __oldval = 0; \
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\
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asm volatile( \
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"1: %0 = memw_locked(%1);\n" \
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" { P0 = cmp.eq(%0,%2);\n" \
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" if (!P0.new) jump:nt 2f; }\n" \
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" memw_locked(%1,p0) = %3;\n" \
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" if (!P0) jump 1b;\n" \
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"2:\n" \
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: "=&r" (__oldval) \
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: "r" (__ptr), "r" (__old), "r" (__new) \
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: "memory", "p0" \
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); \
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__oldval; \
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})
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#endif /* _ASM_CMPXCHG_H */
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