135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Atomic operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/types.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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/* Normal writes in our arch don't clear lock reservations */
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static inline void arch_atomic_set(atomic_t *v, int new)
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{
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asm volatile(
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"1: r6 = memw_locked(%0);\n"
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" memw_locked(%0,p0) = %1;\n"
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" if (!P0) jump 1b;\n"
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:
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: "r" (&v->counter), "r" (new)
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: "memory", "p0", "r6"
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);
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}
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#define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
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#define arch_atomic_read(v) READ_ONCE((v)->counter)
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#define ATOMIC_OP(op) \
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static inline void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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int output; \
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\
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__asm__ __volatile__ ( \
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"1: %0 = memw_locked(%1);\n" \
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" %0 = "#op "(%0,%2);\n" \
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" memw_locked(%1,P3)=%0;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
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{ \
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int output; \
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\
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__asm__ __volatile__ ( \
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"1: %0 = memw_locked(%1);\n" \
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" %0 = "#op "(%0,%2);\n" \
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" memw_locked(%1,P3)=%0;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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); \
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return output; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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int output, val; \
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\
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__asm__ __volatile__ ( \
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"1: %0 = memw_locked(%2);\n" \
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" %1 = "#op "(%0,%3);\n" \
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" memw_locked(%2,P3)=%1;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output), "=&r" (val) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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); \
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return output; \
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}
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(add)
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ATOMIC_OPS(sub)
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#define arch_atomic_add_return arch_atomic_add_return
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#define arch_atomic_sub_return arch_atomic_sub_return
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#define arch_atomic_fetch_add arch_atomic_fetch_add
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#define arch_atomic_fetch_sub arch_atomic_fetch_sub
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(and)
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ATOMIC_OPS(or)
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ATOMIC_OPS(xor)
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#define arch_atomic_fetch_and arch_atomic_fetch_and
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#define arch_atomic_fetch_or arch_atomic_fetch_or
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#define arch_atomic_fetch_xor arch_atomic_fetch_xor
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int __oldval;
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register int tmp;
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asm volatile(
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"1: %0 = memw_locked(%2);"
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" {"
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" p3 = cmp.eq(%0, %4);"
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" if (p3.new) jump:nt 2f;"
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" %1 = add(%0, %3);"
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" }"
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" memw_locked(%2, p3) = %1;"
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" {"
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" if (!p3) jump 1b;"
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" }"
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"2:"
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: "=&r" (__oldval), "=&r" (tmp)
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: "r" (v), "r" (a), "r" (u)
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: "memory", "p3"
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);
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return __oldval;
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}
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#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
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#endif
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