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40e6336d1b
This macro is only valid when CONFIG_TIDSPBRDIGE_DEBUG is enabled and it only prints a log message, it is not a real assertion mechanism like BUG_ON() or WARN_ON(). It is better to remove them: less code to maintain. Signed-off-by: Víctor Manuel Jáquez Leal <vjaquez@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
553 lines
16 KiB
C
553 lines
16 KiB
C
/*
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* tiomap_pwr.c
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Implementation of DSP wake/sleep routines.
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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/* ----------------------------------- Host OS */
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#include <dspbridge/host_os.h>
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#include <plat/dsp.h>
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/* ----------------------------------- DSP/BIOS Bridge */
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#include <dspbridge/dbdefs.h>
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#include <dspbridge/drv.h>
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#include <dspbridge/io_sm.h>
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/* ----------------------------------- Platform Manager */
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#include <dspbridge/brddefs.h>
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#include <dspbridge/dev.h>
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#include <dspbridge/io.h>
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/* ------------------------------------ Hardware Abstraction Layer */
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#include <hw_defs.h>
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#include <hw_mmu.h>
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#include <dspbridge/pwr.h>
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/* ----------------------------------- Bridge Driver */
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#include <dspbridge/dspdeh.h>
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#include <dspbridge/wdt.h>
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/* ----------------------------------- specific to this file */
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#include "_tiomap.h"
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#include "_tiomap_pwr.h"
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#include <mach-omap2/prm-regbits-34xx.h>
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#include <mach-omap2/cm-regbits-34xx.h>
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#define PWRSTST_TIMEOUT 200
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/*
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* ======== handle_constraints_set ========
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* Sets new DSP constraint
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*/
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int handle_constraints_set(struct bridge_dev_context *dev_context,
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void *pargs)
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{
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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u32 *constraint_val;
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struct omap_dsp_platform_data *pdata =
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omap_dspbridge_dev->dev.platform_data;
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constraint_val = (u32 *) (pargs);
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/* Read the target value requested by DSP */
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dev_dbg(bridge, "OPP: %s opp requested = 0x%x\n", __func__,
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(u32) *(constraint_val + 1));
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/* Set the new opp value */
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if (pdata->dsp_set_min_opp)
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(*pdata->dsp_set_min_opp) ((u32) *(constraint_val + 1));
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#endif /* #ifdef CONFIG_TIDSPBRIDGE_DVFS */
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return 0;
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}
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/*
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* ======== handle_hibernation_from_dsp ========
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* Handle Hibernation requested from DSP
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*/
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int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context)
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{
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int status = 0;
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#ifdef CONFIG_PM
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u16 timeout = PWRSTST_TIMEOUT / 10;
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u32 pwr_state;
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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u32 opplevel;
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struct io_mgr *hio_mgr;
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#endif
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struct omap_dsp_platform_data *pdata =
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omap_dspbridge_dev->dev.platform_data;
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pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
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OMAP_POWERSTATEST_MASK;
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/* Wait for DSP to move into OFF state */
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while ((pwr_state != PWRDM_POWER_OFF) && --timeout) {
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if (msleep_interruptible(10)) {
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pr_err("Waiting for DSP OFF mode interrupted\n");
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return -EPERM;
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}
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pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
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OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK;
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}
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if (timeout == 0) {
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pr_err("%s: Timed out waiting for DSP off mode\n", __func__);
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status = -ETIMEDOUT;
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return status;
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} else {
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/* Save mailbox settings */
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omap_mbox_save_ctx(dev_context->mbox);
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/* Turn off DSP Peripheral clocks and DSP Load monitor timer */
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status = dsp_clock_disable_all(dev_context->dsp_per_clks);
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/* Disable wdt on hibernation. */
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dsp_wdt_enable(false);
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if (!status) {
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/* Update the Bridger Driver state */
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dev_context->brd_state = BRD_DSP_HIBERNATION;
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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status =
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dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
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if (!hio_mgr) {
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status = DSP_EHANDLE;
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return status;
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}
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io_sh_msetting(hio_mgr, SHM_GETOPP, &opplevel);
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/*
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* Set the OPP to low level before moving to OFF
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* mode
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*/
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if (pdata->dsp_set_min_opp)
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(*pdata->dsp_set_min_opp) (VDD1_OPP1);
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status = 0;
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#endif /* CONFIG_TIDSPBRIDGE_DVFS */
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}
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}
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#endif
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return status;
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}
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/*
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* ======== sleep_dsp ========
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* Put DSP in low power consuming state.
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*/
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int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd,
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void *pargs)
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{
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int status = 0;
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#ifdef CONFIG_PM
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#ifdef CONFIG_TIDSPBRIDGE_NTFY_PWRERR
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struct deh_mgr *hdeh_mgr;
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#endif /* CONFIG_TIDSPBRIDGE_NTFY_PWRERR */
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u16 timeout = PWRSTST_TIMEOUT / 10;
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u32 pwr_state, target_pwr_state;
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struct omap_dsp_platform_data *pdata =
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omap_dspbridge_dev->dev.platform_data;
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/* Check if sleep code is valid */
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if ((dw_cmd != PWR_DEEPSLEEP) && (dw_cmd != PWR_EMERGENCYDEEPSLEEP))
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return -EINVAL;
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switch (dev_context->brd_state) {
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case BRD_RUNNING:
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omap_mbox_save_ctx(dev_context->mbox);
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if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
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sm_interrupt_dsp(dev_context, MBX_PM_DSPHIBERNATE);
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dev_dbg(bridge, "PM: %s - sent hibernate cmd to DSP\n",
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__func__);
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target_pwr_state = PWRDM_POWER_OFF;
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} else {
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sm_interrupt_dsp(dev_context, MBX_PM_DSPRETENTION);
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target_pwr_state = PWRDM_POWER_RET;
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}
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break;
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case BRD_RETENTION:
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omap_mbox_save_ctx(dev_context->mbox);
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if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
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sm_interrupt_dsp(dev_context, MBX_PM_DSPHIBERNATE);
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target_pwr_state = PWRDM_POWER_OFF;
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} else
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return 0;
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break;
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case BRD_HIBERNATION:
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case BRD_DSP_HIBERNATION:
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/* Already in Hibernation, so just return */
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dev_dbg(bridge, "PM: %s - DSP already in hibernation\n",
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__func__);
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return 0;
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case BRD_STOPPED:
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dev_dbg(bridge, "PM: %s - Board in STOP state\n", __func__);
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return 0;
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default:
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dev_dbg(bridge, "PM: %s - Bridge in Illegal state\n", __func__);
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return -EPERM;
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}
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/* Get the PRCM DSP power domain status */
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pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
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OMAP_POWERSTATEST_MASK;
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/* Wait for DSP to move into target power state */
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while ((pwr_state != target_pwr_state) && --timeout) {
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if (msleep_interruptible(10)) {
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pr_err("Waiting for DSP to Suspend interrupted\n");
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return -EPERM;
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}
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pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
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OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK;
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}
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if (!timeout) {
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pr_err("%s: Timed out waiting for DSP off mode, state %x\n",
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__func__, pwr_state);
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#ifdef CONFIG_TIDSPBRIDGE_NTFY_PWRERR
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dev_get_deh_mgr(dev_context->dev_obj, &hdeh_mgr);
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bridge_deh_notify(hdeh_mgr, DSP_PWRERROR, 0);
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#endif /* CONFIG_TIDSPBRIDGE_NTFY_PWRERR */
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return -ETIMEDOUT;
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} else {
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/* Update the Bridger Driver state */
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if (dsp_test_sleepstate == PWRDM_POWER_OFF)
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dev_context->brd_state = BRD_HIBERNATION;
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else
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dev_context->brd_state = BRD_RETENTION;
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/* Disable wdt on hibernation. */
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dsp_wdt_enable(false);
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/* Turn off DSP Peripheral clocks */
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status = dsp_clock_disable_all(dev_context->dsp_per_clks);
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if (status)
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return status;
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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else if (target_pwr_state == PWRDM_POWER_OFF) {
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/*
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* Set the OPP to low level before moving to OFF mode
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*/
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if (pdata->dsp_set_min_opp)
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(*pdata->dsp_set_min_opp) (VDD1_OPP1);
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}
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#endif /* CONFIG_TIDSPBRIDGE_DVFS */
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}
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#endif /* CONFIG_PM */
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return status;
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}
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/*
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* ======== wake_dsp ========
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* Wake up DSP from sleep.
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*/
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int wake_dsp(struct bridge_dev_context *dev_context, void *pargs)
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{
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int status = 0;
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#ifdef CONFIG_PM
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/* Check the board state, if it is not 'SLEEP' then return */
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if (dev_context->brd_state == BRD_RUNNING ||
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dev_context->brd_state == BRD_STOPPED) {
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/* The Device is in 'RET' or 'OFF' state and Bridge state is not
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* 'SLEEP', this means state inconsistency, so return */
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return 0;
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}
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/* Send a wakeup message to DSP */
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sm_interrupt_dsp(dev_context, MBX_PM_DSPWAKEUP);
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/* Set the device state to RUNNIG */
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dev_context->brd_state = BRD_RUNNING;
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#endif /* CONFIG_PM */
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return status;
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}
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/*
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* ======== dsp_peripheral_clk_ctrl ========
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* Enable/Disable the DSP peripheral clocks as needed..
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*/
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int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
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void *pargs)
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{
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u32 ext_clk = 0;
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u32 ext_clk_id = 0;
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u32 ext_clk_cmd = 0;
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u32 clk_id_index = MBX_PM_MAX_RESOURCES;
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u32 tmp_index;
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u32 dsp_per_clks_before;
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int status = 0;
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dsp_per_clks_before = dev_context->dsp_per_clks;
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ext_clk = (u32) *((u32 *) pargs);
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ext_clk_id = ext_clk & MBX_PM_CLK_IDMASK;
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/* process the power message -- TODO, keep it in a separate function */
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for (tmp_index = 0; tmp_index < MBX_PM_MAX_RESOURCES; tmp_index++) {
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if (ext_clk_id == bpwr_clkid[tmp_index]) {
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clk_id_index = tmp_index;
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break;
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}
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}
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/* TODO -- Assert may be a too hard restriction here.. May be we should
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* just return with failure when the CLK ID does not match */
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if (clk_id_index == MBX_PM_MAX_RESOURCES) {
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/* return with a more meaningfull error code */
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return -EPERM;
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}
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ext_clk_cmd = (ext_clk >> MBX_PM_CLK_CMDSHIFT) & MBX_PM_CLK_CMDMASK;
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switch (ext_clk_cmd) {
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case BPWR_DISABLE_CLOCK:
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status = dsp_clk_disable(bpwr_clks[clk_id_index].clk);
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dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id,
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false);
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if (!status) {
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(dev_context->dsp_per_clks) &=
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(~((u32) (1 << bpwr_clks[clk_id_index].clk)));
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}
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break;
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case BPWR_ENABLE_CLOCK:
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status = dsp_clk_enable(bpwr_clks[clk_id_index].clk);
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dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id, true);
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if (!status)
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(dev_context->dsp_per_clks) |=
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(1 << bpwr_clks[clk_id_index].clk);
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break;
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default:
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dev_dbg(bridge, "%s: Unsupported CMD\n", __func__);
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/* unsupported cmd */
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/* TODO -- provide support for AUTOIDLE Enable/Disable
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* commands */
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}
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return status;
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}
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/*
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* ========pre_scale_dsp========
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* Sends prescale notification to DSP
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*
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*/
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int pre_scale_dsp(struct bridge_dev_context *dev_context, void *pargs)
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{
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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u32 level;
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u32 voltage_domain;
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voltage_domain = *((u32 *) pargs);
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level = *((u32 *) pargs + 1);
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dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
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__func__, voltage_domain, level);
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if ((dev_context->brd_state == BRD_HIBERNATION) ||
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(dev_context->brd_state == BRD_RETENTION) ||
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(dev_context->brd_state == BRD_DSP_HIBERNATION)) {
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dev_dbg(bridge, "OPP: %s IVA in sleep. No message to DSP\n");
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return 0;
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} else if ((dev_context->brd_state == BRD_RUNNING)) {
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/* Send a prenotificatio to DSP */
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dev_dbg(bridge, "OPP: %s sent notification to DSP\n", __func__);
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sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_PRENOTIFY);
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return 0;
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} else {
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return -EPERM;
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}
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#endif /* #ifdef CONFIG_TIDSPBRIDGE_DVFS */
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return 0;
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}
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/*
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* ========post_scale_dsp========
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* Sends postscale notification to DSP
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*
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*/
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int post_scale_dsp(struct bridge_dev_context *dev_context,
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void *pargs)
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{
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int status = 0;
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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u32 level;
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u32 voltage_domain;
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struct io_mgr *hio_mgr;
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status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
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if (!hio_mgr)
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return -EFAULT;
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voltage_domain = *((u32 *) pargs);
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level = *((u32 *) pargs + 1);
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dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
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__func__, voltage_domain, level);
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if ((dev_context->brd_state == BRD_HIBERNATION) ||
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(dev_context->brd_state == BRD_RETENTION) ||
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(dev_context->brd_state == BRD_DSP_HIBERNATION)) {
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/* Update the OPP value in shared memory */
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io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
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dev_dbg(bridge, "OPP: %s IVA in sleep. Wrote to shm\n",
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__func__);
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} else if ((dev_context->brd_state == BRD_RUNNING)) {
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/* Update the OPP value in shared memory */
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io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
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/* Send a post notification to DSP */
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sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_POSTNOTIFY);
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dev_dbg(bridge, "OPP: %s wrote to shm. Sent post notification "
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"to DSP\n", __func__);
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} else {
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status = -EPERM;
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}
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#endif /* #ifdef CONFIG_TIDSPBRIDGE_DVFS */
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return status;
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}
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void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
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{
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struct cfg_hostres *resources;
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int status = 0;
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u32 iva2_grpsel;
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u32 mpu_grpsel;
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struct dev_object *hdev_object = NULL;
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struct bridge_dev_context *bridge_context = NULL;
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hdev_object = (struct dev_object *)drv_get_first_dev_object();
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if (!hdev_object)
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return;
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status = dev_get_bridge_context(hdev_object, &bridge_context);
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if (!bridge_context)
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return;
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resources = bridge_context->resources;
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if (!resources)
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return;
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switch (clock_id) {
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case BPWR_GP_TIMER5:
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iva2_grpsel = readl(resources->per_pm_base + 0xA8);
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mpu_grpsel = readl(resources->per_pm_base + 0xA4);
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if (enable) {
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iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
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mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
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} else {
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mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
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iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
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}
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writel(iva2_grpsel, resources->per_pm_base + 0xA8);
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writel(mpu_grpsel, resources->per_pm_base + 0xA4);
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break;
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case BPWR_GP_TIMER6:
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iva2_grpsel = readl(resources->per_pm_base + 0xA8);
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mpu_grpsel = readl(resources->per_pm_base + 0xA4);
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if (enable) {
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iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
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mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
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} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_GP_TIMER7:
|
|
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_GP_TIMER8:
|
|
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_MCBSP1:
|
|
iva2_grpsel = readl(resources->core_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->core_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->core_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->core_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_MCBSP2:
|
|
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_MCBSP3:
|
|
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_MCBSP4:
|
|
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
case BPWR_MCBSP5:
|
|
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
|
|
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
|
|
if (enable) {
|
|
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
|
|
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
|
|
} else {
|
|
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
|
|
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
|
|
}
|
|
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
|
|
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
|
|
break;
|
|
}
|
|
}
|