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![William Breathitt Gray](/assets/img/avatar_default.png)
Replace verbose implementation in get_multiple/set_multiple callbacks with for_each_set_clump8 macro to simplify code and improve clarity. Link: http://lkml.kernel.org/r/0de53d7021b2d6db10294473cd8a1b6102bcec94.1570641097.git.vilhelm.gray@gmail.com Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Lukas Wunner <lukas@wunner.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Morten Hein Tiljeset <morten.tiljeset@prevas.dk> Cc: Phil Reid <preid@electromag.com.au> Cc: Rasmus Villemoes <linux@rasmusvillemoes.dk> Cc: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
318 lines
9.2 KiB
C
318 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the Diamond Systems GPIO-MM
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This driver supports the following Diamond Systems devices: GPIO-MM and
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* GPIO-MM-12.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#define GPIOMM_EXTENT 8
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#define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)
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static unsigned int base[MAX_NUM_GPIOMM];
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static unsigned int num_gpiomm;
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module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
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MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
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/**
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* struct gpiomm_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @control: Control registers state
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* @lock: synchronization lock to prevent I/O race conditions
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* @base: base port address of the GPIO device
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*/
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struct gpiomm_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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unsigned char control[2];
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spinlock_t lock;
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unsigned int base;
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};
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static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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if (gpiommgpio->io_state[port] & mask)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int gpiomm_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
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unsigned long flags;
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unsigned int control;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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gpiommgpio->io_state[io_port] |= 0xF0;
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gpiommgpio->control[control_port] |= BIT(3);
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} else {
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gpiommgpio->io_state[io_port] |= 0x0F;
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gpiommgpio->control[control_port] |= BIT(0);
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}
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} else {
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gpiommgpio->io_state[io_port] |= 0xFF;
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if (io_port == 0 || io_port == 3)
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gpiommgpio->control[control_port] |= BIT(4);
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else
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gpiommgpio->control[control_port] |= BIT(1);
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}
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control = BIT(7) | gpiommgpio->control[control_port];
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outb(control, control_addr);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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return 0;
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}
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static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
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const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
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unsigned long flags;
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unsigned int control;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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gpiommgpio->io_state[io_port] &= 0x0F;
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gpiommgpio->control[control_port] &= ~BIT(3);
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} else {
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gpiommgpio->io_state[io_port] &= 0xF0;
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gpiommgpio->control[control_port] &= ~BIT(0);
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}
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} else {
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gpiommgpio->io_state[io_port] &= 0x00;
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if (io_port == 0 || io_port == 3)
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gpiommgpio->control[control_port] &= ~BIT(4);
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else
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gpiommgpio->control[control_port] &= ~BIT(1);
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}
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if (value)
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gpiommgpio->out_state[io_port] |= mask;
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else
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gpiommgpio->out_state[io_port] &= ~mask;
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control = BIT(7) | gpiommgpio->control[control_port];
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outb(control, control_addr);
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outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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return 0;
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}
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static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int in_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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unsigned int port_state;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(gpiommgpio->io_state[port] & mask)) {
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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return -EINVAL;
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}
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port_state = inb(gpiommgpio->base + in_port);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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return !!(port_state & mask);
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}
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static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
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static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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unsigned int port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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port_addr = gpiommgpio->base + ports[offset / 8];
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port_state = inb(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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return 0;
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}
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static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int out_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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if (value)
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gpiommgpio->out_state[port] |= mask;
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else
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gpiommgpio->out_state[port] &= ~mask;
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outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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}
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static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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unsigned int port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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index = offset / 8;
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port_addr = gpiommgpio->base + ports[index];
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* update output state data and set device gpio register */
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gpiommgpio->out_state[index] &= ~gpio_mask;
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gpiommgpio->out_state[index] |= bitmask;
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outb(gpiommgpio->out_state[index], port_addr);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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}
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}
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#define GPIOMM_NGPIO 48
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static const char *gpiomm_names[GPIOMM_NGPIO] = {
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"Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
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"Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
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"Port 1B4", "Port 1B5", "Port 1B6", "Port 1B7", "Port 1C0", "Port 1C1",
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"Port 1C2", "Port 1C3", "Port 1C4", "Port 1C5", "Port 1C6", "Port 1C7",
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"Port 2A0", "Port 2A1", "Port 2A2", "Port 2A3", "Port 2A4", "Port 2A5",
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"Port 2A6", "Port 2A7", "Port 2B0", "Port 2B1", "Port 2B2", "Port 2B3",
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"Port 2B4", "Port 2B5", "Port 2B6", "Port 2B7", "Port 2C0", "Port 2C1",
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"Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
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};
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static int gpiomm_probe(struct device *dev, unsigned int id)
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{
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struct gpiomm_gpio *gpiommgpio;
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const char *const name = dev_name(dev);
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int err;
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gpiommgpio = devm_kzalloc(dev, sizeof(*gpiommgpio), GFP_KERNEL);
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if (!gpiommgpio)
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return -ENOMEM;
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if (!devm_request_region(dev, base[id], GPIOMM_EXTENT, name)) {
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dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
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base[id], base[id] + GPIOMM_EXTENT);
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return -EBUSY;
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}
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gpiommgpio->chip.label = name;
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gpiommgpio->chip.parent = dev;
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gpiommgpio->chip.owner = THIS_MODULE;
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gpiommgpio->chip.base = -1;
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gpiommgpio->chip.ngpio = GPIOMM_NGPIO;
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gpiommgpio->chip.names = gpiomm_names;
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gpiommgpio->chip.get_direction = gpiomm_gpio_get_direction;
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gpiommgpio->chip.direction_input = gpiomm_gpio_direction_input;
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gpiommgpio->chip.direction_output = gpiomm_gpio_direction_output;
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gpiommgpio->chip.get = gpiomm_gpio_get;
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gpiommgpio->chip.get_multiple = gpiomm_gpio_get_multiple;
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gpiommgpio->chip.set = gpiomm_gpio_set;
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gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
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gpiommgpio->base = base[id];
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spin_lock_init(&gpiommgpio->lock);
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err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
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if (err) {
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dev_err(dev, "GPIO registering failed (%d)\n", err);
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return err;
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}
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/* initialize all GPIO as output */
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outb(0x80, base[id] + 3);
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outb(0x00, base[id]);
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outb(0x00, base[id] + 1);
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outb(0x00, base[id] + 2);
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outb(0x80, base[id] + 7);
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outb(0x00, base[id] + 4);
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outb(0x00, base[id] + 5);
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outb(0x00, base[id] + 6);
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return 0;
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}
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static struct isa_driver gpiomm_driver = {
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.probe = gpiomm_probe,
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.driver = {
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.name = "gpio-mm"
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},
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};
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module_isa_driver(gpiomm_driver, num_gpiomm);
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MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
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MODULE_DESCRIPTION("Diamond Systems GPIO-MM GPIO driver");
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MODULE_LICENSE("GPL v2");
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