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![Wei Yongjun](/assets/img/avatar_default.png)
In case of error, the function devm_platform_ioremap_resource_byname()
returns ERR_PTR() and never returns NULL. The NULL test in the return
value check should be replaced with IS_ERR().
Fixes: 4195926aed
("gpio: Add support for IDT 79RC3243x GPIO controller")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
206 lines
5.2 KiB
C
206 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Driver for IDT/Renesas 79RC3243x Interrupt Controller */
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define IDT_PIC_IRQ_PEND 0x00
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#define IDT_PIC_IRQ_MASK 0x08
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#define IDT_GPIO_DIR 0x00
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#define IDT_GPIO_DATA 0x04
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#define IDT_GPIO_ILEVEL 0x08
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#define IDT_GPIO_ISTAT 0x0C
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struct idt_gpio_ctrl {
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struct gpio_chip gc;
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void __iomem *pic;
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void __iomem *gpio;
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u32 mask_cache;
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};
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static void idt_gpio_dispatch(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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struct irq_chip *host_chip = irq_desc_get_chip(desc);
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unsigned int bit, virq;
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unsigned long pending;
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chained_irq_enter(host_chip, desc);
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pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND);
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pending &= ~ctrl->mask_cache;
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for_each_set_bit(bit, &pending, gc->ngpio) {
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virq = irq_linear_revmap(gc->irq.domain, bit);
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if (virq)
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generic_handle_irq(virq);
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}
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chained_irq_exit(host_chip, desc);
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}
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static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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unsigned int sense = flow_type & IRQ_TYPE_SENSE_MASK;
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unsigned long flags;
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u32 ilevel;
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/* hardware only supports level triggered */
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if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH))
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return -EINVAL;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL);
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if (sense & IRQ_TYPE_LEVEL_HIGH)
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ilevel |= BIT(d->hwirq);
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else if (sense & IRQ_TYPE_LEVEL_LOW)
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ilevel &= ~BIT(d->hwirq);
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writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL);
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irq_set_handler_locked(d, handle_level_irq);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static void idt_gpio_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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writel(~BIT(d->hwirq), ctrl->gpio + IDT_GPIO_ISTAT);
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}
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static void idt_gpio_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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ctrl->mask_cache |= BIT(d->hwirq);
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writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void idt_gpio_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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ctrl->mask_cache &= ~BIT(d->hwirq);
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writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int idt_gpio_irq_init_hw(struct gpio_chip *gc)
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{
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struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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/* Mask interrupts. */
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ctrl->mask_cache = 0xffffffff;
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writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
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return 0;
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}
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static struct irq_chip idt_gpio_irqchip = {
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.name = "IDTGPIO",
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.irq_mask = idt_gpio_mask,
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.irq_ack = idt_gpio_ack,
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.irq_unmask = idt_gpio_unmask,
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.irq_set_type = idt_gpio_irq_set_type
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};
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static int idt_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct gpio_irq_chip *girq;
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struct idt_gpio_ctrl *ctrl;
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unsigned int parent_irq;
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int ngpios;
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int ret;
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ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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ctrl->gpio = devm_platform_ioremap_resource_byname(pdev, "gpio");
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if (IS_ERR(ctrl->gpio))
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return PTR_ERR(ctrl->gpio);
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ctrl->gc.parent = dev;
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ret = bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->gpio + IDT_GPIO_DATA,
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NULL, NULL, ctrl->gpio + IDT_GPIO_DIR, NULL, 0);
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if (ret) {
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dev_err(dev, "bgpio_init failed\n");
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return ret;
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}
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ret = device_property_read_u32(dev, "ngpios", &ngpios);
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if (!ret)
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ctrl->gc.ngpio = ngpios;
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if (device_property_read_bool(dev, "interrupt-controller")) {
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ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic");
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if (IS_ERR(ctrl->pic))
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return PTR_ERR(ctrl->pic);
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parent_irq = platform_get_irq(pdev, 0);
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if (!parent_irq)
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return -EINVAL;
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girq = &ctrl->gc.irq;
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girq->chip = &idt_gpio_irqchip;
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girq->init_hw = idt_gpio_irq_init_hw;
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girq->parent_handler = idt_gpio_dispatch;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, girq->num_parents,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = parent_irq;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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}
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return devm_gpiochip_add_data(&pdev->dev, &ctrl->gc, ctrl);
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}
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static const struct of_device_id idt_gpio_of_match[] = {
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{ .compatible = "idt,32434-gpio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, idt_gpio_of_match);
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static struct platform_driver idt_gpio_driver = {
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.probe = idt_gpio_probe,
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.driver = {
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.name = "idt3243x-gpio",
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.of_match_table = idt_gpio_of_match,
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},
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};
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module_platform_driver(idt_gpio_driver);
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MODULE_DESCRIPTION("IDT 79RC3243x GPIO/PIC Driver");
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MODULE_AUTHOR("Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
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MODULE_LICENSE("GPL");
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