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![Marc Zyngier](/assets/img/avatar_default.png)
Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
322 lines
9.3 KiB
C
322 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/gpio/driver.h>
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#include <linux/irq.h>
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#include <linux/minmax.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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/*
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* Total register block size is 0x1C for one bank of four ports (A, B, C, D).
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* An optional second bank, with ports E, F, G, and H, may be present, starting
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* at register offset 0x1C.
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*/
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/*
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* Pin select: (0) "normal", (1) "dedicate peripheral"
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* Not used on RTL8380/RTL8390, peripheral selection is managed by control bits
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* in the peripheral registers.
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*/
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#define REALTEK_GPIO_REG_CNR 0x00
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/* Clear bit (0) for input, set bit (1) for output */
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#define REALTEK_GPIO_REG_DIR 0x08
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#define REALTEK_GPIO_REG_DATA 0x0C
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/* Read bit for IRQ status, write 1 to clear IRQ */
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#define REALTEK_GPIO_REG_ISR 0x10
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/* Two bits per GPIO in IMR registers */
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#define REALTEK_GPIO_REG_IMR 0x14
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#define REALTEK_GPIO_REG_IMR_AB 0x14
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#define REALTEK_GPIO_REG_IMR_CD 0x18
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#define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0)
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#define REALTEK_GPIO_IRQ_EDGE_FALLING 1
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#define REALTEK_GPIO_IRQ_EDGE_RISING 2
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#define REALTEK_GPIO_IRQ_EDGE_BOTH 3
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#define REALTEK_GPIO_MAX 32
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#define REALTEK_GPIO_PORTS_PER_BANK 4
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/**
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* realtek_gpio_ctrl - Realtek Otto GPIO driver data
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*
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* @gc: Associated gpio_chip instance
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* @base: Base address of the register block for a GPIO bank
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* @lock: Lock for accessing the IRQ registers and values
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* @intr_mask: Mask for interrupts lines
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* @intr_type: Interrupt type selection
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*
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* Because the interrupt mask register (IMR) combines the function of IRQ type
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* selection and masking, two extra values are stored. @intr_mask is used to
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* mask/unmask the interrupts for a GPIO port, and @intr_type is used to store
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* the selected interrupt types. The logical AND of these values is written to
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* IMR on changes.
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*/
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struct realtek_gpio_ctrl {
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struct gpio_chip gc;
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void __iomem *base;
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raw_spinlock_t lock;
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u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
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u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
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};
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/* Expand with more flags as devices with other quirks are added */
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enum realtek_gpio_flags {
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/*
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* Allow disabling interrupts, for cases where the port order is
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* unknown. This may result in a port mismatch between ISR and IMR.
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* An interrupt would appear to come from a different line than the
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* line the IRQ handler was assigned to, causing uncaught interrupts.
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*/
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GPIO_INTERRUPTS_DISABLED = BIT(0),
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};
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static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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return container_of(gc, struct realtek_gpio_ctrl, gc);
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}
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/*
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* Normal port order register access
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*
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* Port information is stored with the first port at offset 0, followed by the
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* second, etc. Most registers store one bit per GPIO and use a u8 value per
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* port. The two interrupt mask registers store two bits per GPIO, so use u16
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* values.
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*/
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static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl,
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unsigned int port, u16 irq_type, u16 irq_mask)
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{
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iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port);
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}
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static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl,
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unsigned int port, u8 mask)
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{
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iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port);
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}
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static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port)
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{
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return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port);
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}
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/* Set the rising and falling edge mask bits for a GPIO port pin */
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static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value)
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{
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return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin;
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}
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static void realtek_gpio_irq_ack(struct irq_data *data)
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{
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struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
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irq_hw_number_t line = irqd_to_hwirq(data);
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unsigned int port = line / 8;
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unsigned int port_pin = line % 8;
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realtek_gpio_clear_isr(ctrl, port, BIT(port_pin));
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}
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static void realtek_gpio_irq_unmask(struct irq_data *data)
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{
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struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
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unsigned int line = irqd_to_hwirq(data);
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unsigned int port = line / 8;
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unsigned int port_pin = line % 8;
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unsigned long flags;
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u16 m;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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m = ctrl->intr_mask[port];
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m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
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ctrl->intr_mask[port] = m;
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realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void realtek_gpio_irq_mask(struct irq_data *data)
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{
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struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
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unsigned int line = irqd_to_hwirq(data);
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unsigned int port = line / 8;
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unsigned int port_pin = line % 8;
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unsigned long flags;
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u16 m;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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m = ctrl->intr_mask[port];
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m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
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ctrl->intr_mask[port] = m;
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realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
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unsigned int line = irqd_to_hwirq(data);
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unsigned int port = line / 8;
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unsigned int port_pin = line % 8;
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unsigned long flags;
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u16 type, t;
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switch (flow_type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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type = REALTEK_GPIO_IRQ_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_RISING:
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type = REALTEK_GPIO_IRQ_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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type = REALTEK_GPIO_IRQ_EDGE_BOTH;
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break;
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default:
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return -EINVAL;
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}
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irq_set_handler_locked(data, handle_edge_irq);
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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t = ctrl->intr_type[port];
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t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
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t |= realtek_gpio_imr_bits(port_pin, type);
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ctrl->intr_type[port] = t;
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realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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static void realtek_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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unsigned int lines_done;
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unsigned int port_pin_count;
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unsigned long status;
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int offset;
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chained_irq_enter(irq_chip, desc);
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for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {
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status = realtek_gpio_read_isr(ctrl, lines_done / 8);
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port_pin_count = min(gc->ngpio - lines_done, 8U);
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for_each_set_bit(offset, &status, port_pin_count)
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generic_handle_domain_irq(gc->irq.domain, offset);
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}
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chained_irq_exit(irq_chip, desc);
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}
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static int realtek_gpio_irq_init(struct gpio_chip *gc)
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{
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struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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unsigned int port;
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for (port = 0; (port * 8) < gc->ngpio; port++) {
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realtek_gpio_write_imr(ctrl, port, 0, 0);
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realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));
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}
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return 0;
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}
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static struct irq_chip realtek_gpio_irq_chip = {
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.name = "realtek-otto-gpio",
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.irq_ack = realtek_gpio_irq_ack,
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.irq_mask = realtek_gpio_irq_mask,
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.irq_unmask = realtek_gpio_irq_unmask,
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.irq_set_type = realtek_gpio_irq_set_type,
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};
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static const struct of_device_id realtek_gpio_of_match[] = {
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{
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.compatible = "realtek,otto-gpio",
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.data = (void *)GPIO_INTERRUPTS_DISABLED,
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},
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{
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.compatible = "realtek,rtl8380-gpio",
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},
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{
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.compatible = "realtek,rtl8390-gpio",
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
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static int realtek_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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unsigned int dev_flags;
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struct gpio_irq_chip *girq;
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struct realtek_gpio_ctrl *ctrl;
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u32 ngpios;
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int err, irq;
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ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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dev_flags = (unsigned int) device_get_match_data(dev);
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ngpios = REALTEK_GPIO_MAX;
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device_property_read_u32(dev, "ngpios", &ngpios);
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if (ngpios > REALTEK_GPIO_MAX) {
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dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",
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REALTEK_GPIO_MAX);
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return -EINVAL;
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}
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ctrl->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ctrl->base))
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return PTR_ERR(ctrl->base);
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raw_spin_lock_init(&ctrl->lock);
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err = bgpio_init(&ctrl->gc, dev, 4,
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ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,
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ctrl->base + REALTEK_GPIO_REG_DIR, NULL,
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BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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if (err) {
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dev_err(dev, "unable to init generic GPIO");
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return err;
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}
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ctrl->gc.ngpio = ngpios;
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ctrl->gc.owner = THIS_MODULE;
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irq = platform_get_irq_optional(pdev, 0);
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if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
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girq = &ctrl->gc.irq;
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girq->chip = &realtek_gpio_irq_chip;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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girq->parent_handler = realtek_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, girq->num_parents,
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sizeof(*girq->parents), GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = irq;
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girq->init_hw = realtek_gpio_irq_init;
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}
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return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
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}
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static struct platform_driver realtek_gpio_driver = {
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.driver = {
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.name = "realtek-otto-gpio",
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.of_match_table = realtek_gpio_of_match,
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},
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.probe = realtek_gpio_probe,
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};
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module_platform_driver(realtek_gpio_driver);
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MODULE_DESCRIPTION("Realtek Otto GPIO support");
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MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
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MODULE_LICENSE("GPL v2");
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