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![Marc Zyngier](/assets/img/avatar_default.png)
Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
407 lines
9.8 KiB
C
407 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* GPIO interface for Intel Poulsbo SCH
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*
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* Copyright (c) 2010 CompuLab Ltd
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* Author: Denis Turischev <denis@compulab.co.il>
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*/
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci_ids.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#define GEN 0x00
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#define GIO 0x04
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#define GLV 0x08
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#define GTPE 0x0c
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#define GTNE 0x10
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#define GGPE 0x14
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#define GSMI 0x18
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#define GTS 0x1c
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#define CORE_BANK_OFFSET 0x00
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#define RESUME_BANK_OFFSET 0x20
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/*
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* iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
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* Document Number: 328195-001
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*/
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#define GPE0E_GPIO 14
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struct sch_gpio {
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struct gpio_chip chip;
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struct irq_chip irqchip;
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spinlock_t lock;
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unsigned short iobase;
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unsigned short resume_base;
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/* GPE handling */
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u32 gpe;
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acpi_gpe_handler gpe_handler;
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};
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static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
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unsigned int reg)
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{
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unsigned int base = CORE_BANK_OFFSET;
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if (gpio >= sch->resume_base) {
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gpio -= sch->resume_base;
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base = RESUME_BANK_OFFSET;
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}
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return base + reg + gpio / 8;
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}
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static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
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{
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if (gpio >= sch->resume_base)
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gpio -= sch->resume_base;
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return gpio % 8;
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}
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static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
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{
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unsigned short offset, bit;
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u8 reg_val;
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
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return reg_val;
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}
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static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
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int val)
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{
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unsigned short offset, bit;
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u8 reg_val;
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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reg_val = inb(sch->iobase + offset);
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if (val)
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outb(reg_val | BIT(bit), sch->iobase + offset);
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else
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outb((reg_val & ~BIT(bit)), sch->iobase + offset);
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}
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static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GIO, 1);
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spin_unlock_irqrestore(&sch->lock, flags);
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return 0;
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}
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static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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return sch_gpio_reg_get(sch, gpio_num, GLV);
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}
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static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GLV, val);
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spin_unlock_irqrestore(&sch->lock, flags);
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}
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static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
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int val)
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GIO, 0);
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spin_unlock_irqrestore(&sch->lock, flags);
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/*
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* according to the datasheet, writing to the level register has no
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* effect when GPIO is programmed as input.
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* Actually the the level register is read-only when configured as input.
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* Thus presetting the output level before switching to output is _NOT_ possible.
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* Hence we set the level after configuring the GPIO as output.
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* But we cannot prevent a short low pulse if direction is set to high
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* and an external pull-up is connected.
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*/
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sch_gpio_set(gc, gpio_num, val);
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return 0;
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}
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static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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if (sch_gpio_reg_get(sch, gpio_num, GIO))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static const struct gpio_chip sch_gpio_chip = {
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.label = "sch_gpio",
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.owner = THIS_MODULE,
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.direction_input = sch_gpio_direction_in,
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.get = sch_gpio_get,
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.direction_output = sch_gpio_direction_out,
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.set = sch_gpio_set,
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.get_direction = sch_gpio_get_direction,
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};
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static int sch_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sch_gpio *sch = gpiochip_get_data(gc);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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unsigned long flags;
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int rising, falling;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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rising = 1;
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falling = 0;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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rising = 0;
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falling = 1;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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rising = 1;
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falling = 1;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
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sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
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irq_set_handler_locked(d, handle_edge_irq);
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spin_unlock_irqrestore(&sch->lock, flags);
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return 0;
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}
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static void sch_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sch_gpio *sch = gpiochip_get_data(gc);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GTS, 1);
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spin_unlock_irqrestore(&sch->lock, flags);
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}
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static void sch_irq_mask_unmask(struct irq_data *d, int val)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sch_gpio *sch = gpiochip_get_data(gc);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GGPE, val);
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spin_unlock_irqrestore(&sch->lock, flags);
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}
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static void sch_irq_mask(struct irq_data *d)
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{
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sch_irq_mask_unmask(d, 0);
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}
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static void sch_irq_unmask(struct irq_data *d)
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{
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sch_irq_mask_unmask(d, 1);
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}
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static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
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{
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struct sch_gpio *sch = context;
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struct gpio_chip *gc = &sch->chip;
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unsigned long core_status, resume_status;
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unsigned long pending;
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unsigned long flags;
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int offset;
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u32 ret;
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spin_lock_irqsave(&sch->lock, flags);
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core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
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resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
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spin_unlock_irqrestore(&sch->lock, flags);
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pending = (resume_status << sch->resume_base) | core_status;
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for_each_set_bit(offset, &pending, sch->chip.ngpio)
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generic_handle_domain_irq(gc->irq.domain, offset);
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/* Set returning value depending on whether we handled an interrupt */
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ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
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/* Acknowledge GPE to ACPICA */
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ret |= ACPI_REENABLE_GPE;
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return ret;
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}
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static void sch_gpio_remove_gpe_handler(void *data)
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{
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struct sch_gpio *sch = data;
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acpi_disable_gpe(NULL, sch->gpe);
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acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
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}
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static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
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{
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struct device *dev = sch->chip.parent;
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acpi_status status;
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status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
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sch->gpe_handler, sch);
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if (ACPI_FAILURE(status)) {
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dev_err(dev, "Failed to install GPE handler for %u: %s\n",
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sch->gpe, acpi_format_exception(status));
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return -ENODEV;
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}
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status = acpi_enable_gpe(NULL, sch->gpe);
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if (ACPI_FAILURE(status)) {
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dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
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sch->gpe, acpi_format_exception(status));
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acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
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return -ENODEV;
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}
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return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
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}
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static int sch_gpio_probe(struct platform_device *pdev)
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{
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struct gpio_irq_chip *girq;
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struct sch_gpio *sch;
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struct resource *res;
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int ret;
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sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
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if (!sch)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!res)
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return -EBUSY;
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if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
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pdev->name))
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return -EBUSY;
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spin_lock_init(&sch->lock);
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sch->iobase = res->start;
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sch->chip = sch_gpio_chip;
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sch->chip.label = dev_name(&pdev->dev);
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sch->chip.parent = &pdev->dev;
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switch (pdev->id) {
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case PCI_DEVICE_ID_INTEL_SCH_LPC:
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sch->resume_base = 10;
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sch->chip.ngpio = 14;
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/*
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* GPIO[6:0] enabled by default
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* GPIO7 is configured by the CMC as SLPIOVR
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* Enable GPIO[9:8] core powered gpios explicitly
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*/
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sch_gpio_reg_set(sch, 8, GEN, 1);
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sch_gpio_reg_set(sch, 9, GEN, 1);
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/*
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* SUS_GPIO[2:0] enabled by default
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* Enable SUS_GPIO3 resume powered gpio explicitly
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*/
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sch_gpio_reg_set(sch, 13, GEN, 1);
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break;
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case PCI_DEVICE_ID_INTEL_ITC_LPC:
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sch->resume_base = 5;
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sch->chip.ngpio = 14;
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break;
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case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
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sch->resume_base = 21;
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sch->chip.ngpio = 30;
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break;
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case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
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sch->resume_base = 2;
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sch->chip.ngpio = 8;
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break;
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default:
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return -ENODEV;
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}
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platform_set_drvdata(pdev, sch);
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sch->irqchip.name = "sch_gpio";
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sch->irqchip.irq_ack = sch_irq_ack;
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sch->irqchip.irq_mask = sch_irq_mask;
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sch->irqchip.irq_unmask = sch_irq_unmask;
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sch->irqchip.irq_set_type = sch_irq_type;
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girq = &sch->chip.irq;
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girq->chip = &sch->irqchip;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->parent_handler = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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/* GPE setup is optional */
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sch->gpe = GPE0E_GPIO;
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sch->gpe_handler = sch_gpio_gpe_handler;
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ret = sch_gpio_install_gpe_handler(sch);
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if (ret)
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dev_warn(&pdev->dev, "Can't setup GPE, no IRQ support\n");
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return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
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}
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static struct platform_driver sch_gpio_driver = {
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.driver = {
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.name = "sch_gpio",
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},
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.probe = sch_gpio_probe,
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};
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module_platform_driver(sch_gpio_driver);
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MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
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MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:sch_gpio");
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