mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 16:29:59 +00:00
![Thomas Gleixner](/assets/img/avatar_default.png)
API updates: - Treewide conversion to generic_handle_domain_irq() for anything that looks like a chained interrupt controller - Update the irqdomain documentation - Use of bitmap_zalloc() throughout the tree New functionalities: - Support for GICv3 EPPI partitions Fixes: - Qualcomm PDC hierarchy fixes - Yet another priority decoding fix for the GICv3 pseudo-NMIs - Fix the apple-aic driver irq_eoi() callback to always unmask the interrupt - Properly handle edge interrupts on loongson-pch-pic - Let the mtk-sysirq driver advertise IRQCHIP_SKIP_SET_WAKE -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAmEqIhgPHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDjPkP/Rtp6WNZ1QUfJWmHovnh/Wc6ob1DXcBwi9nX hy4miIJ1SWuez9G49RlQAiXZoB28B6KKCKKmouiqu7ke7WUhifS0K1ej188wjxRX dqRG+m9yBAqKSr0lyWLB5VVCc8XBz4oZTc28n585gHiXfAPv7u0EzW+zNrnloLU5 NrAj6ppGFUzVT0VxRqcurbymE6OwRWjc3D+z/PhtHZ4SFOhft95CXgsdvMklqyLj wwiuZ0Dhj5EruSP/Z7DzbbXnMNmte3HC2/cUNPYkho4/rk+2gVnYv5kVdfPHKQCY Wjti/kvuPC3hdTvdw8g7VQfP63R3clZhcQ8s+myoeX5LWzyAHpoxAtdsbX7oVsgs aKyrFhddEFVuiFizYyweS89pL0kCkTob8/zlGeuhRiVRTZ3+kG7Zf2UTTnN1ZdLw 2lMolghiGk4LYJfr83+CDZyYP/VGHDCthfrmd//l39P2wJhkuCDbbeKaElLGWvUt abnPf0buCRqMAJe7vh0GHCx7290nEh2IqyHR4AYRVhRaN7bfAXdZH9Xp6ZGT25Fz uORgUbGAyhd5Ics/7twE4qeOkfJ6fxwgXsOlx90EfgVYyDJ1sBHNx8Buo2z8Bl/2 rwCsW49kU7yX/wp11sJctR72RuLKC23dxS6z7aSWkRc6k3u+8xl2eeLIN59FNrKZ ToTdbXEQ =bdm2 -----END PGP SIGNATURE----- Merge tag 'irqchip-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier: - API updates: - Treewide conversion to generic_handle_domain_irq() for anything that looks like a chained interrupt controller - Update the irqdomain documentation - Use of bitmap_zalloc() throughout the tree - New functionalities: - Support for GICv3 EPPI partitions - Fixes: - Qualcomm PDC hierarchy fixes - Yet another priority decoding fix for the GICv3 pseudo-NMIs - Fix the apple-aic driver irq_eoi() callback to always unmask the interrupt - Properly handle edge interrupts on loongson-pch-pic - Let the mtk-sysirq driver advertise IRQCHIP_SKIP_SET_WAKE Link: https://lore.kernel.org/r/20210828121013.2647964-1-maz@kernel.org
343 lines
8.8 KiB
C
343 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TQ-Systems TQMx86 PLD GPIO driver
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*
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* Based on vendor driver by:
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* Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#define TQMX86_NGPIO 8
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#define TQMX86_NGPO 4 /* 0-3 - output */
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#define TQMX86_NGPI 4 /* 4-7 - input */
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#define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
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#define TQMX86_GPIODD 0 /* GPIO Data Direction Register */
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#define TQMX86_GPIOD 1 /* GPIO Data Register */
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#define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */
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#define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */
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#define TQMX86_GPII_FALLING BIT(0)
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#define TQMX86_GPII_RISING BIT(1)
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#define TQMX86_GPII_MASK (BIT(0) | BIT(1))
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#define TQMX86_GPII_BITS 2
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struct tqmx86_gpio_data {
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struct gpio_chip chip;
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struct irq_chip irq_chip;
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void __iomem *io_base;
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int irq;
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raw_spinlock_t spinlock;
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u8 irq_type[TQMX86_NGPI];
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};
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static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg)
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{
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return ioread8(gd->io_base + reg);
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}
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static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
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unsigned int reg)
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{
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iowrite8(val, gd->io_base + reg);
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}
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static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
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return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset));
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}
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static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
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unsigned long flags;
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u8 val;
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raw_spin_lock_irqsave(&gpio->spinlock, flags);
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val = tqmx86_gpio_read(gpio, TQMX86_GPIOD);
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if (value)
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val |= BIT(offset);
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else
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val &= ~BIT(offset);
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tqmx86_gpio_write(gpio, val, TQMX86_GPIOD);
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raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
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}
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static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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/* Direction cannot be changed. Validate is an input. */
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if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
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return 0;
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else
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return -EINVAL;
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}
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static int tqmx86_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset,
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int value)
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{
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/* Direction cannot be changed, validate is an output */
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if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
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return -EINVAL;
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tqmx86_gpio_set(chip, offset, value);
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return 0;
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}
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static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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if (TQMX86_DIR_INPUT_MASK & BIT(offset))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static void tqmx86_gpio_irq_mask(struct irq_data *data)
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{
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unsigned int offset = (data->hwirq - TQMX86_NGPO);
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(
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irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u8 gpiic, mask;
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mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
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raw_spin_lock_irqsave(&gpio->spinlock, flags);
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gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
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gpiic &= ~mask;
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tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
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raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
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}
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static void tqmx86_gpio_irq_unmask(struct irq_data *data)
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{
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unsigned int offset = (data->hwirq - TQMX86_NGPO);
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(
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irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u8 gpiic, mask;
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mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
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raw_spin_lock_irqsave(&gpio->spinlock, flags);
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gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
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gpiic &= ~mask;
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gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS);
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tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
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raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
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}
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static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(
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irq_data_get_irq_chip_data(data));
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unsigned int offset = (data->hwirq - TQMX86_NGPO);
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unsigned int edge_type = type & IRQF_TRIGGER_MASK;
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unsigned long flags;
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u8 new_type, gpiic;
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switch (edge_type) {
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case IRQ_TYPE_EDGE_RISING:
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new_type = TQMX86_GPII_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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new_type = TQMX86_GPII_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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new_type = TQMX86_GPII_FALLING | TQMX86_GPII_RISING;
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break;
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default:
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return -EINVAL; /* not supported */
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}
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gpio->irq_type[offset] = new_type;
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raw_spin_lock_irqsave(&gpio->spinlock, flags);
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gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
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gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS));
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gpiic |= new_type << (offset * TQMX86_GPII_BITS);
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tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
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raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
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return 0;
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}
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static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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unsigned long irq_bits;
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int i = 0;
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u8 irq_status;
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chained_irq_enter(irq_chip, desc);
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irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
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tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
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irq_bits = irq_status;
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for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
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generic_handle_domain_irq(gpio->chip.irq.domain,
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i + TQMX86_NGPO);
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chained_irq_exit(irq_chip, desc);
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}
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/* Minimal runtime PM is needed by the IRQ subsystem */
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static int __maybe_unused tqmx86_gpio_runtime_suspend(struct device *dev)
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{
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return 0;
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}
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static int __maybe_unused tqmx86_gpio_runtime_resume(struct device *dev)
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{
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return 0;
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}
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static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = {
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SET_RUNTIME_PM_OPS(tqmx86_gpio_runtime_suspend,
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tqmx86_gpio_runtime_resume, NULL)
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};
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static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip,
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unsigned long *valid_mask,
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unsigned int ngpios)
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{
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/* Only GPIOs 4-7 are valid for interrupts. Clear the others */
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clear_bit(0, valid_mask);
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clear_bit(1, valid_mask);
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clear_bit(2, valid_mask);
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clear_bit(3, valid_mask);
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}
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static int tqmx86_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tqmx86_gpio_data *gpio;
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struct gpio_chip *chip;
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struct gpio_irq_chip *girq;
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void __iomem *io_base;
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struct resource *res;
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int ret, irq;
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irq = platform_get_irq_optional(pdev, 0);
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if (irq < 0 && irq != -ENXIO)
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return irq;
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!res) {
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dev_err(&pdev->dev, "Cannot get I/O\n");
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return -ENODEV;
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}
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io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
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if (!io_base)
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return -ENOMEM;
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gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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raw_spin_lock_init(&gpio->spinlock);
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gpio->io_base = io_base;
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tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD);
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platform_set_drvdata(pdev, gpio);
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chip = &gpio->chip;
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chip->label = "gpio-tqmx86";
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chip->owner = THIS_MODULE;
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chip->can_sleep = false;
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chip->base = -1;
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chip->direction_input = tqmx86_gpio_direction_input;
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chip->direction_output = tqmx86_gpio_direction_output;
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chip->get_direction = tqmx86_gpio_get_direction;
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chip->get = tqmx86_gpio_get;
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chip->set = tqmx86_gpio_set;
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chip->ngpio = TQMX86_NGPIO;
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chip->parent = pdev->dev.parent;
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pm_runtime_enable(&pdev->dev);
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if (irq > 0) {
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struct irq_chip *irq_chip = &gpio->irq_chip;
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u8 irq_status;
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irq_chip->name = chip->label;
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irq_chip->parent_device = &pdev->dev;
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irq_chip->irq_mask = tqmx86_gpio_irq_mask;
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irq_chip->irq_unmask = tqmx86_gpio_irq_unmask;
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irq_chip->irq_set_type = tqmx86_gpio_irq_set_type;
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/* Mask all interrupts */
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tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC);
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/* Clear all pending interrupts */
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irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
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tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
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girq = &chip->irq;
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girq->chip = irq_chip;
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girq->parent_handler = tqmx86_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(&pdev->dev, 1,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents) {
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ret = -ENOMEM;
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goto out_pm_dis;
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}
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girq->parents[0] = irq;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_simple_irq;
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girq->init_valid_mask = tqmx86_init_irq_valid_mask;
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}
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ret = devm_gpiochip_add_data(dev, chip, gpio);
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if (ret) {
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dev_err(dev, "Could not register GPIO chip\n");
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goto out_pm_dis;
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}
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dev_info(dev, "GPIO functionality initialized with %d pins\n",
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chip->ngpio);
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return 0;
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out_pm_dis:
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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static struct platform_driver tqmx86_gpio_driver = {
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.driver = {
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.name = "tqmx86-gpio",
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.pm = &tqmx86_gpio_dev_pm_ops,
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},
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.probe = tqmx86_gpio_probe,
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};
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module_platform_driver(tqmx86_gpio_driver);
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MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver");
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MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:tqmx86-gpio");
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