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![Alexandru Ardelean](/assets/img/avatar_default.png)
The handling of the return value from devm_gpiochip_add_data() is a bit redundant. It prints messages on error and success cases. While the success message may be useful, it is more in the area of log spam, and these can be printed with other forms of kernel logging. This change does a direct return with devm_gpiochip_add_data() in the probe function. The platform_set_drvdata() is needed, as this driver uses the stored private date in the PM suspend/resume routines. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
209 lines
5.5 KiB
C
209 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AppliedMicro X-Gene SoC GPIO Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Author: Feng Kan <fkan@apm.com>.
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*/
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#include <linux/acpi.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/gpio/driver.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#define GPIO_SET_DR_OFFSET 0x0C
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#define GPIO_DATA_OFFSET 0x14
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#define GPIO_BANK_STRIDE 0x0C
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#define XGENE_GPIOS_PER_BANK 16
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#define XGENE_MAX_GPIO_BANKS 3
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#define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
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#define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
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#define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
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struct xgene_gpio {
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struct gpio_chip chip;
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void __iomem *base;
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spinlock_t lock;
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u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
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};
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static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct xgene_gpio *chip = gpiochip_get_data(gc);
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unsigned long bank_offset;
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u32 bit_offset;
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bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
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}
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static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct xgene_gpio *chip = gpiochip_get_data(gc);
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unsigned long bank_offset;
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u32 setval, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
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setval = ioread32(chip->base + bank_offset);
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if (val)
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setval |= BIT(bit_offset);
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else
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setval &= ~BIT(bit_offset);
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iowrite32(setval, chip->base + bank_offset);
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}
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static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct xgene_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__xgene_gpio_set(gc, offset, val);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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struct xgene_gpio *chip = gpiochip_get_data(gc);
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unsigned long bank_offset, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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if (ioread32(chip->base + bank_offset) & BIT(bit_offset))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct xgene_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags, bank_offset;
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u32 dirval, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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spin_lock_irqsave(&chip->lock, flags);
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dirval = ioread32(chip->base + bank_offset);
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dirval |= BIT(bit_offset);
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iowrite32(dirval, chip->base + bank_offset);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int xgene_gpio_dir_out(struct gpio_chip *gc,
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unsigned int offset, int val)
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{
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struct xgene_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags, bank_offset;
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u32 dirval, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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spin_lock_irqsave(&chip->lock, flags);
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dirval = ioread32(chip->base + bank_offset);
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dirval &= ~BIT(bit_offset);
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iowrite32(dirval, chip->base + bank_offset);
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__xgene_gpio_set(gc, offset, val);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static __maybe_unused int xgene_gpio_suspend(struct device *dev)
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{
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struct xgene_gpio *gpio = dev_get_drvdata(dev);
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unsigned long bank_offset;
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unsigned int bank;
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for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
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bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
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gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
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}
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return 0;
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}
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static __maybe_unused int xgene_gpio_resume(struct device *dev)
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{
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struct xgene_gpio *gpio = dev_get_drvdata(dev);
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unsigned long bank_offset;
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unsigned int bank;
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for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
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bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
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iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
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}
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
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static int xgene_gpio_probe(struct platform_device *pdev)
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{
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struct xgene_gpio *gpio;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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gpio->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(gpio->base))
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return PTR_ERR(gpio->base);
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gpio->chip.ngpio = XGENE_MAX_GPIOS;
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spin_lock_init(&gpio->lock);
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gpio->chip.parent = &pdev->dev;
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gpio->chip.get_direction = xgene_gpio_get_direction;
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gpio->chip.direction_input = xgene_gpio_dir_in;
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gpio->chip.direction_output = xgene_gpio_dir_out;
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gpio->chip.get = xgene_gpio_get;
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gpio->chip.set = xgene_gpio_set;
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gpio->chip.label = dev_name(&pdev->dev);
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gpio->chip.base = -1;
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platform_set_drvdata(pdev, gpio);
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return devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
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}
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static const struct of_device_id xgene_gpio_of_match[] = {
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{ .compatible = "apm,xgene-gpio", },
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{},
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};
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#ifdef CONFIG_ACPI
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static const struct acpi_device_id xgene_gpio_acpi_match[] = {
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{ "APMC0D14", 0 },
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{ },
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};
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#endif
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static struct platform_driver xgene_gpio_driver = {
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.driver = {
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.name = "xgene-gpio",
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.of_match_table = xgene_gpio_of_match,
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.acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
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.pm = &xgene_gpio_pm,
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},
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.probe = xgene_gpio_probe,
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};
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builtin_platform_driver(xgene_gpio_driver);
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